
Parameter
Min
Typ
Max
Units
Test Condition
SIGNAL INPUTS
Voltage Amplitude
1.8
2.0
2.2
V rms
Sinusoidal Waveforms, Differential
SIN to SINLO, COS to COSLO
Frequency
3
20
kHz
Input Bias Current
100
nA
VIN = 2
± 10% V rms
Input Impedance
1.0
M
VIN = 2
± 10% V rms
Common-Mode Volts
1
100
mV peak
CMV @ SINLO, COSLO w.r.t.
CMRR
60
dB
AGND @ 10 kHz
REFERENCE INPUT
Voltage Amplitude
1.8
2.0
3.35
V rms
Sinusoidal Waveform
Frequency
3
20
kHz
Input Bias Current
100
nA
Input Impedance
100
k
Permissible Phase Shift
–10
+10
Degrees
Relative to SIN, COS Inputs
CONVERTER DYNAMICS
Bandwidth
700
840
1000
Hz
Maximum Tracking Rate
500
rps
Maximum VCO Rate (CLKOUT)
2.048
MHz
Settling Time
1
° Step
2
7
ms
179
° Step
20
ms
ACCURACY
Angular Accuracy
2
±10.6 + 1 LSB arc min
Repeatability3
1
LSB
VELOCITY OUTPUT
Scaling
120
150
180
rps/V dc
Output Voltage at 500 rps
±2.78
±3.33
±4.17
V dc
Load Drive Capability
±250
AV
OUT =
±2.5 V dc (typ), R
L
≥ 10 k
LOGIC INPUTS SCLK,
CS
Input High Voltage (VINH)
3.5
V dc
VDD = +5 V dc, VSS = –5 V dc
Input Low Voltage (VINL)
1.5
V dc
VDD = +5 V dc, VSS = –5 V dc
Input Current (IIN)
10
A
Input Capacitance
10
pF
LOGIC OUTPUTS DATA, A, B,
4
NM, CLKOUT, DIR
VDD = +5 V dc, VSS = –5 V dc
Output High Voltage
4.0
V dc
IOH = 1 mA
Output Low Voltage
1.0
V dc
IOL = 1 mA
0.4
V dc
IOL = 400 A
SERIAL CLOCK (SCLK)
SCLK Input Rate
2
MHz
NORTH MARKER CONTROL (NMC)
90
°
+4.75
+5.0
+5.25
V dc
North Marker Width Relative to
180
°
–0.75
DGND
+0.75
V dc
“A” Cycle
360
°
–4.75
–5.0
–5.25
V dc
POWER SUPPLIES
VDD
+4.75
+5.00
+5.25
V dc
VSS
–4.75
–5.00
–5.25
V dc
IDD
10
mA
ISS
10
mA
NOTES
1If the tolerance on signal inputs =
±5%, then CMV = 200 mV.
21 LSB = 5.3 arc minute.
3Specified at constant temperature.
4Output load drive capability.
Specifications subject to change without notice.
AD2S90–SPECIFICATIONS
(VDD = +5 V
5%, VSS = –5 V
5%, AGND = DGND = 0 V, TA = –40 C to +85 C unless
otherwise noted)
REV. D
–2–