参数资料
| 型号： | AD5025BRUZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/28页 |
| 文件大小： | 0K |
| 描述： | IC DAC DUAL 12BIT SPI 14TSSOP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 96 |
| 系列： | nanoDAC™ |
| 设置时间： | 5.8µs |
| 位数： | 12 |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 2 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 13.5mW |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 14-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 14-TSSOP |
| 包装： | 管件 |
| 输出数目和类型： | 2 电压，单极；2 电压，双极 |
| 采样率（每秒）： | * |
| 产品目录页面： | 781 (CN2011-ZH PDF) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页当前第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页
AD5025/AD5045/AD5065
Rev. 0 | Page 22 of 28
POWER-DOWN LOCKOUT
The AD5025/AD5045/AD5065 contain a digital input pin, PDL.
When activated, the power-down lockout pin (PDL) disables
software shutdown under any circumstances. The user should
hardwire the PDL pin to a logic low (thus preventing subsequent
software power-down) or logic high (the part can be placed in
power-down mode over the serial interface). If the user transitions
the PDL pin from logic high to a logic low during a valid write
sequence, the device responds immediately and the current
write sequence is aborted. Note the following PDL features.
PDL During a Write Sequence
If a PDL is generated (that is, a high-to-low transition) while a
valid write sequence is ongoing, the write is aborted. The user
must rewrite the current write command again.
PDL While DACs in Power-Down Mode
If a PDL is generated while the DAC(s) are in power-down
mode, the DAC(s) come out of power-down (that is, all power-
down bits are reset to 0000) to the last voltage output correspond-
ing to the last valid stored DAC value. While PDL remains active,
software power-down is disabled.
PDL Low to High Transition
After PDL is taken from a low to a high state, all DAC channels
remain in normal mode, and the user must reissue a software
power-down command to the control register to power down
the required channels.
Transitioning PDL from a low to a high disables the feature
immediately.
If PDL and CLR are generated at the same time, the CLR signal
causes the DAC register to change as per the clear code register,
and the DACs come out of power-down.
If PDL, CLR, and LDAC are generated at the same time, CLR
has higher precedence over LDAC and PDL.
The user is recommended to hardwire the pin to a logic high or
low, thereby either enabling or disabling the feature.
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the board.
The printed circuit board (PCB) containing the AD5025/AD5045/
AD5065 should have separate analog and digital sections. If the
AD5025/AD5045/AD5065 are in a system where other devices
require an AGND-to-DGND connection, the connection should
be made at one point only. This ground point should be as close
as possible to the AD5025/AD5045/AD5065.
Bypass the power supply to the AD5025/AD5045/AD5065 with
10 μF and 0.1 μF capacitors. The capacitors should physically be
as close as possible to the device, with the 0.1 μF capacitor
ideally right up against the device. The 10 μF capacitors are the
tantalum bead type. It is important that the 0.1 μF capacitor has
low effective series resistance (ESR) and low effective series
inductance (ESI), which is typical of common ceramic types of
capacitors. This 0.1 μF capacitor provides a low impedance path
to ground for high frequencies caused by transient currents due
to internal logic switching.
The power supply line should have as large a trace as possible to
provide a low impedance path and reduce glitch effects on the
supply line. Shield clocks and other fast switching digital signals
from other parts of the board by digital ground. Avoid crossover
of digital and analog signals if possible. When traces cross on
opposite sides of the board, ensure that they run at right angles
to each other to reduce feedthrough effects through the board.
The best board layout technique is the microstrip technique,
where the component side of the board is dedicated to the
ground plane only and the signal traces are placed on the solder
side. However, this is not always possible with a 2-layer board.
相关PDF资料 |
PDF描述 |
|---|---|
| AD9760ARUZ | IC DAC 10BIT 125MSPS 28-TSSOP |
| AD5667RBRMZ-1 | IC DAC NANO 16BIT DUAL 10-MSOP |
| VE-262-MW-F1 | CONVERTER MOD DC/DC 15V 100W |
| VE-261-MW-F4 | CONVERTER MOD DC/DC 12V 100W |
| VE-261-MW-F3 | CONVERTER MOD DC/DC 12V 100W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD5025BRUZ-REEL7 | 功能描述:IC DAC DUAL 12BIT SPI 14TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:nanoDAC™ 产品培训模块:LTC263x 12-, 10-, and 8-Bit VOUT DAC Family 特色产品:LTC2636 - Octal 12-/10-/8-Bit SPI VOUT DACs with 10ppm/°C Reference 标准包装:91 系列:- 设置时间:4µs 位数:10 数据接口:MICROWIRE?，串行，SPI? 转换器数目:8 电压电源:单电源 功率耗散（最大）:2.7mW 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:14-WFDFN 裸露焊盘 供应商设备封装:14-DFN-EP（4x3） 包装:管件 输出数目和类型:8 电压，单极 采样率（每秒）:* |
| AD-5028S | 制造商:BOTHHAND 制造商全称:Bothhand USA, LP. 功能描述:ADSL LINE TRANSFORMER |
| AD50294 | 制造商:Analog Devices 功能描述: |
| AD50294-1 | 制造商:Analog Devices 功能描述: |
| AD503 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:N-CHANNEL JFET |
发布紧急采购，3分钟左右您将得到回复。