参数资料
型号: AD5061YRJZ-1500RL7
厂商: Analog Devices Inc
文件页数: 18/20页
文件大小: 0K
描述: IC DAC 16BIT SPI/SRL SOT23-8
产品培训模块: Data Converter Fundamentals
DAC Architectures
标准包装: 1
系列: nanoDAC™
设置时间: 4µs
位数: 16
数据接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
电压电源: 单电源
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: SOT-23-8
供应商设备封装: SOT-23-8
包装: 标准包装
输出数目和类型: 1 电压,单极;1 电压,双极
采样率(每秒): 1.3M
其它名称: AD5061YRJZ-1500RL7DKR
AD5061
Rev. B | Page 7 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD5061
TOP VIEW
(Not to Scale)
VOUT
SYNC
18
AGND
SCLK
27
DIN
DACGND
36
04
76
2-
0
03
VREF
45
VDD
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
DIN
Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.
2
VDD
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V and VDD should be decoupled to GND.
3
VREF
Reference Voltage Input.
4
VOUT
Analog Output Voltage from DAC.
5
AGND
Ground Reference Point for Analog Circuitry.
6
DACGND
Ground Input to the DAC.
7
SYNC
Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC
goes low, it enables the input shift register and data is transferred in on the falling edges of the following clocks.
The DAC is updated following the 24th clock cycle unless SYNC is taken high before this edge, in which case the
rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC.
8
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can
be transferred at rates up to 30 MHz.
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