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参数资料
| 型号： | AD5245BRJ100-R2 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字电位计 |
| 英文描述： | CAP CERAMIC 10PF 50V NP0 0402 |
| 中文描述： | 100K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO8 |
| 封装： | 2.90 X 3 MM, MO-178BA, SOT-23, 8 PIN |
| 文件页数： | 13/16页 |
| 文件大小： | 995K |
| 代理商： | AD5245BRJ100-R2 |
AD5245
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A proportional to the input voltage at
A-to-B. Unlike the polarity of V
DD
to GND, which must be
positive, voltage across A-B, W-A, and W-B can be at either
polarity.
Rev. 0 | Page 13 of 16
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper-to-B starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the
voltage applied across terminal AB divided by the 256 positions
of the potentiometer divider. The general equation defining the
output voltage at V
W
with respect to ground for any valid input
voltage applied to terminals A and B is
B
A
W
V
D
V
D
256
D
(
V
256
256
)
+
=
(3)
For a more accurate calculation, which includes the effect of
wiper resistance, V
W
, can be found as
B
WA
R
A
WB
R
W
V
D
(
V
D
(
D
(
V
256
)
256
)
)
+
=
(4)
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors R
WA
and R
WB
and not the
absolute values. Therefore, the temperature drift reduces to
15 ppm/°C.
I
2
C COMPATIBLE 2-WIRE SERIAL BUS
The first byte of the AD5245 is a slave address byte (see Table 5
and Table 6). It has a 7-bit slave address and a R/W bit. The six
MSBs of the slave address are 010110, and the following bit is
determined by the state of the AD0 pin of the device. AD0
allows the user to place up to two of the I
2
C compatible devices
on one bus.
The 2-wire I
2
C serial bus protocol operates as follows:
1.
The master initiates data transfer by establishing a START
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high (see Figure 37). The
following byte is the slave address byte, which consists of
the 7-bit slave address followed by an R/W bit (this bit
determines whether data will be read from or written to
the slave device).
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is termed the acknowledge bit). At
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from
its serial register. If the R/W bit is high, the master will read
from the slave device. On the other hand, if the R/W bit is
low, the master will write to the slave device.
2.
A write operation contains an extra instruction byte that a
read operation does not contain. Such an instruction byte
in write mode follows the slave address byte. The first bit
(MSB) of the instruction byte is a don’t care.
The second MSB, RS, is the midscale reset. A logic high on
this bit moves the wiper to the center tap where R
WA
= R
WB
.
This feature effectively writes over the contents of the
register, and thus, when taken out of reset mode, the RDAC
will remain at midscale.
The third MSB, SD, is a shutdown bit. A logic high causes
an open circuit at terminal A while shorting the wiper to
terminal B. This operation yields almost 0 in rheostat
mode or 0 V in potentiometer mode. It is important to note
that the shutdown operation does not disturb the contents
of the register. When brought out of shutdown, the
previous setting will be applied to the RDAC. Also, during
shutdown, new settings can be programmed. When the
part is returned from shutdown, the corresponding VR
setting will be applied to the RDAC.
The remainder of the bits in the instruction byte are don’t
cares (see Table 5).
3.
After acknowledging the instruction byte, the last byte in
write mode is the data byte. Data is transmitted over the
serial bus in sequences of nine clock pulses (eight data bits
followed by an acknowledge bit). The transitions on the
SDA line must occur during the low period of SCL and
remain stable during the high period of SCL (see Table 5).
4.
In the read mode, the data byte follows immediately after
the acknowledgment of the slave address byte. Data is
transmitted over the serial bus in sequences of nine clock
pulses (a slight difference with the write mode, where there
are eight data bits followed by an acknowledge bit).
Similarly, the transitions on the SDA line must occur
during the low period of SCL and remain stable during the
high period of SCL (see Figure 38).
5.
When all data bits have been read or written, a STOP
condition is established by the master. A STOP condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In write mode, the master will pull the SDA
line high during the tenth clock pulse to establish a STOP
condition (see Figure 37). In read mode, the master will
issue a No Acknowledge for the ninth clock pulse (i.e., the
SDA line remains high). The master will then bring the
SDA line low before the tenth clock pulse which goes high
to establish a STOP condition (see Figure 38).
相关PDF资料 |
PDF描述 |
|---|---|
| AD5245BRJ100-RL7 | 256-Position I2C Compatible Digital Potentiometer |
| AD5245BRJ50-R2 | 256-Position I2C Compatible Digital Potentiometer |
| AD5245BRJ50-RL7 | 256-Position I2C Compatible Digital Potentiometer |
| AD5245EVAL | 256-Position I2C Compatible Digital Potentiometer |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD5245BRJ100-RL7 | 制造商:AD 制造商全称:Analog Devices 功能描述:256-Position I2C Compatible Digital Potentiometer |
| AD5245BRJ10-R2 | 制造商:Analog Devices 功能描述:IC DIGITAL POT. 8-BIT I2C |
| AD5245BRJ10-RL7 | 制造商:Analog Devices 功能描述:Digital Potentiometer 256POS 10KOhm Single 8-Pin SOT-23 T/R |
| AD5245BRJ5 | 制造商:AD 制造商全称:Analog Devices 功能描述:256-Position I2C-Compatible Digital Potentiometer |
| AD5245BRJ50 | 制造商:AD 制造商全称:Analog Devices 功能描述:256-Position I2C-Compatible Digital Potentiometer |
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