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| 型号： | AD5255BRU25 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字电位计 |
| 英文描述： | 3-Channel Digital Potentiometer with Nonvolatile Memory |
| 中文描述： | TRIPLE 25K DIGITAL POTENTIOMETER, INCREMENT/DECREMENT CONTROL INTERFACE, 512 POSITIONS, PDSO24 |
| 封装： | MO-153AD, TSSOP-24 |
| 文件页数： | 5/20页 |
| 文件大小： | 626K |
| 代理商： | AD5255BRU25 |
AD5255
ELECTRICAL CHARACTERISTICS
Single Supply: V
DD
= 3 V to 5.5 V and 40°C < T
A
< +85°C, unless otherwise noted.
Dual Supply: V
DD
= +2.25 V or +2.75 V , V
SS
= 2.25 V or 2.75 V and 40°C < T
A
< + 85°C, unless otherwise noted.
Table 2.
Parameter
Symbol
DYNAMIC CHARACTERISTICS
5, 7
Bandwidth 3 dB
BW
Total Harmonic Distortion
THD
W
V
W
Settling Time
t
S
Rev. 0 | Page 5 of 20
Conditions
V
DD
/V
SS
= ±2.5 V, R
AB
= 25 k/250 k
V
A
= 1 V rms, V
B
= 0 V, f = 1 kHz
V
A
= V
DD
, V
B
= 0 V,
V
W
= 0.50% error band,
code 0x000 to 0x100, R
AB
= 25 k/250 k
R
AB
= 25 k/250 k, T
A
= 25°C
V
A
= V
DD
, V
B
= 0 V, measure VW with
adjacent RDAC making full-scale
change
Signal input at A0 and measure output
at W1, f = 1 kHz
Min
Typ
1
125/12
0.05
4/36
Max
Unit
kHz
%
μs
Resistor Noise Spectral Density
Digital Crosstalk
e
N_WB
C
T
14/45
80
nV√Hz
dB
Analog Crosstalk
C
AT
72
dB
INTERFACE TIMING CHARACTERISTICS
(apply to all parts) (Notes
8, 9
)
SCL Clock Frequency
t
BUF
Bus Free Time between Stop and
Start
t
HD;STA
Hold Time (Repeated Start)
f
SCL
t
1
1.3
400
kHz
μs
t
2
After this period the first clock pulse is
generated
600
ns
t
LOW
Low Period of SCL Clock
t
HIGH
High Period of SCL Clock
t
SU;STA
Setup Time for Start Condition
t
HD;DAT
Data Hold Time
t
SU;DAT
Data Setup Time
t
R
Rise Time of Both SDA and SCL
Signals
t
F
Fall Time of Both SDA and SCL
Signals
t
SU;STO
Setup Time for Stop Condition
EEMEM Data Storing Time
EEMEM Data Restoring Time at
Power-On
EEMEM Data Restoring Time on
Restore
Command or Reset Operation
EEMEM Data Rewritable Time
FLASH/EE MEMORY RELIABILITY
Endurance
10
Data Retention
11
t
3
t
4
t
5
t
6
t
7
t
8
1.3
0.6
600
100
50
900
300
μs
μs
ns
ns
ns
ns
t
9
300
ns
t
10
t
EEMEM_STORE
t
EEMEM_RESTORE1
600
26
360
ns
ms
μs
t
EEMEM_RESTORE2
360
μs
t
EEMEM_REWRITE
55°C
540
100
100
μs
kcycles
years
1
Typical represent average readings at 25°C, V
DD
= 5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions.
3
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V.
4
Resistor Terminals A, B, W have no limitations on polarity with respect to each other.
5
Guaranteed by design and not subject to production test.
6
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
7
All dynamic characteristics use V
DD
= 5 V.
8
Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
9
See the timing diagram for location of measured values.
10
Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at 40°C, +25°C, and +85°C, typical endurance at 25°C is 700,000 cycles.
11
Retention lifetime equivalent at junction temperature (T
J
) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV
derates with junction temperature.
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