参数资料
| 型号： | AD5263BRU50 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/28页 |
| 文件大小： | 0K |
| 描述： | IC POT QUAD 50K 256POS 24-TSSOP |
| 标准包装： | 62 |
| 接片： | 256 |
| 电阻（欧姆）： | 50k |
| 电路数： | 4 |
| 温度系数： | 标准值 30 ppm/°C |
| 存储器类型： | 易失 |
| 接口： | I²C，SPI（芯片选择，设备位址） |
| 电源电压： | 2.7 V ~ 5.5 V，5 V ~ 15 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 管件 |
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AD5263
Data Sheet
Rev. F | Page 22 of 28
VLOGIC POWER SUPPLY
The AD5263 is capable of operating at high voltages beyond the
internal logic levels, which are limited to operation at 5 V. As a
result, VL always needs to be tied to a separate 2.7 V to 5.5 V source
to ensure proper digital signal levels. Logic levels must be limited to
VL, regardless of VDD. In addition, VL should always be less than
or equal to VDD.
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum-lead length
layout design. The leads to the input should be as direct as possible
with a minimum conductor length. Ground paths should have
low resistance and low inductance.
Similarly, it is also a good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to
the device should be bypassed with 0.01 F to 0.1 F ceramic
disc or chip capacitors. Low ESR 1 F to 10 F tantalum or
electrolytic capacitors should also be applied at the supplies to
minimize any transient disturbance and low frequency ripple
(see Figure 55). Notice the digital ground should also be joined
remotely to the analog ground at one point to minimize the
ground bounce.
03142-
055
GND
VSS
VDD
AD5263
VSS
VDD
C1
0.1F
C2
0.1F
C3
10F
C4
10F
+
Figure 55. Power Supply Bypassing
RDAC CIRCUIT SIMULATION MODEL
The internal parasitic capacitances and the external capacitive loads
dominate the ac characteristics of the RDACs. Configured as a
potentiometer divider, the –3 dB bandwidth of the AD5263 (20 k
resistor) measures 300 kHz at half scale. Figure 22 provides the
large signal BODE plot characteristics of the three available
resistor versions: 20 k, 50 k, and 200 k. A parasitic simulation
model is shown in Figure 56. The following code provides a
macro model net list for the 20 k RDAC.
03142-
069
20k
CA
W
25pF
RDAC
A
B
CB
CW
25pF
55pF
Figure 56. RDAC Circuit Simulation Model for RDAC = 20 k
Listing 1. Macro Model Net List for RDAC
.PARAM D=256, RDAC=20E3
*
.SUBCKT DPOT (A,W,B)
*
CA
A
0
25E-12
RWA
A
W
{(1-D/256)*RDAC+60}
CW
W
0
55E-12
RWB
W
B
{D/256*RDAC+60}
CB
B
0
25E-12
*
.ENDS DPOT
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD5263BRU50-REEL7 | 功能描述:IC DGTL POT QUAD 256POS 24-TSSOP RoHS:否 类别:集成电路 (IC) >> 数据采集 - 数字电位器 系列:- 标准包装:3,000 系列:DPP 接片:32 电阻（欧姆）:10k 电路数:1 温度系数:标准值 300 ppm/°C 存储器类型:非易失 接口:3 线串行（芯片选择，递增，增/减） 电源电压:2.5 V ~ 6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-WFDFN 裸露焊盘 供应商设备封装:8-TDFN（2x3） 包装:带卷 (TR) |
| AD5263BRUZ20 | 功能描述:IC DGTL POT QUAD 20K 24-TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数字电位器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 接片:256 电阻（欧姆）:100k 电路数:1 温度系数:标准值 35 ppm/°C 存储器类型:非易失 接口:3 线串口 电源电压:2.7 V ~ 5.25 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-WDFN 裸露焊盘 供应商设备封装:8-TDFN-EP（3x3） 包装:剪切带 (CT) 产品目录页面:1399 (CN2011-ZH PDF) 其它名称:MAX5423ETA+TCT |
| AD5263BRUZ20 | 制造商:Analog Devices 功能描述:DIG POT, QUAD, 256, 15V, 20KOHM, 24TSSOP; End To End Resistance:20kohm; Track Taper:Linear; Resistance Tolerance: 30%; Supply Voltage Min:4.5V; Supply Voltage Max:16.5V; Potentiometer IC Case Style:TSSOP; No. of Pins:24; No. of ;RoHS Compliant: Yes |
| AD5263BRUZ200 | 功能描述:IC POT QUAD 200K 256POS 24-TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数字电位器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 接片:256 电阻（欧姆）:100k 电路数:1 温度系数:标准值 35 ppm/°C 存储器类型:非易失 接口:3 线串口 电源电压:2.7 V ~ 5.25 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-WDFN 裸露焊盘 供应商设备封装:8-TDFN-EP（3x3） 包装:剪切带 (CT) 产品目录页面:1399 (CN2011-ZH PDF) 其它名称:MAX5423ETA+TCT |
| AD5263BRUZ200-R7 | 制造商:Analog Devices 功能描述:QUAD, 15 V, 256-POSITION DIGITAL POTENTIOMETER WITH PIN-SELE - Tape and Reel |
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