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| 型号： | AD5280BRU200 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字电位计 |
| 英文描述： | 32-Tap. Nonvolatile. Linear-Taper Digital Potentiometers in SOT23 |
| 中文描述： | 200K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO14 |
| 封装： | MO-153AB-1, TSSOP-14 |
| 文件页数： | 5/10页 |
| 文件大小： | 156K |
| 代理商： | AD5280BRU200 |
PRELIMINARY TECHNICAL DATA
AD5280/AD5282
Programmable address bit for multiple
package decoding. Bits AD0 & AD1
provide 4 possible addresses.
Programmable address bit for multiple
package decoding. Bits AD0 & AD1
provide 4 possible addresses.
Common Ground
Negative power supply, specified for
operation from 0 to -5V
Logic Supply Voltage, needs to be same
voltage as the digital logic controlling the
AD5282.
Resistor terminal B
2
Wiper terminal W
2
Resistor terminal A
2
REV PrE 12 MAR 02
Information contained in this Product Concept Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final
product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 382-3107; FAX 408 382-2721; email; walt.heinzer@analog.com
5
TABLE 2:
AD5282 PIN Function Descriptions
Pin
Name
Description
1
O1
Logic Output terminal O1
2
A
1
Resistor terminal A
1
3
W
1
Wiper terminal W
1
4
B
1
Resistor terminal B
1
5
V
DD
Positive power supply, specified for
operation from +5 to +15V.
6
SHDN
Active Low, Asynchronous connection of
the wiper W to terminal B, and open
circuit of terminal A. RDAC register
contents unchanged.
7
SCL
Serial Clock Input
8
SDA
Serial Data Input/Output
9
AD0
10
AD1
11
12
GND
V
SS
13
V
L
14
15
16
B
2
W
2
A
2
t
4
SDA
SCL
P
S
Sr
P
t
1
t
2
t
3
t
5
t
6
t
7
t
8
t
8
t
9
t
10
Figure 1. Detail Timing Diagram
Data of AD5280/AD5282 is accepted from the I
2
C bus in the following serial format:
S
0
1
0
1
1
A
D
1
A
D
0
R/
W
A
A
/
B
R
S
S
D
O
1
O
2
X
X
X
A
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
P
Where:
S
= Start Condition
P
= Stop Condition
A
= Acknowledge
X
= Don’t Care
AD1
,
AD0
= Package pin programmable address bits
Slave Address Byte
Instruction Byte
Data Byte
R/
W
= Read Enable at High and Write Enable at Low
A
/B
= RDAC sub address select. “Zero” for RDAC1 and “One” for RDAC2
SD
= Shutdown, same as
SHDN
pin operation except inverse logic
O2
,
O1
= Output logic pin latched values
D7,D6,D5,D4,D3,D2,D1,D0
= Data Bits
SCL
SDA
1
9
1
0
1
1
0
AD0
AD1
R/
W
ACK. BY
AD5280
D7
D6
D5
D3
D4
D0
D1
D2
1
9
AD5280
A/
B
RS
SD
O2
O1
X
X
X
1
9
AD5280
FRAME 1
Slave Address Byte
START BY
MASTER
FRAME 2
Instruction Byte
FRAME 3
Data Byte
Figure 2. Writing to the RDAC Register
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