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参数资料
| 型号： | AD5304 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | 2.5 V to 5.5 V, 500 uA, Quad Voltage Output 8-/10-/12-Bit DACs in 10-Lead microSOIC |
| 中文描述： | 2.5 V至5.5 V，500微安，四路电压输出数模转换器8-/10-/12-Bit在10引脚microSOIC |
| 文件页数： | 11/15页 |
| 文件大小： | 226K |
| 代理商： | AD5304 |
AD5304/AD5314/AD5324
–11–
REV. B
When the
PD
bit is set to 1, all DACs work normally with a
typical power consumption of 600
μ
A at 5 V (500
μ
A at 3 V).
However, in power-down mode, the supply current falls to 200 nA
at 5 V (80 nA at 3 V) when all DACs are powered down. Not
only does the supply current drop, but the output stage is also
internally switched from the output of the amplifier making it
open-circuit. This has the advantage that the output is three-
stated while the part is in power-down mode, and provides a
defined input condition for whatever is connected to the output
of the DAC amplifier. The output stage is illustrated in Figure 32.
The bias generator, the output amplifier, the resistor string, and
all other associated linear circuitry are all shut down when the
power-down mode is activated. However, the contents of the
registers are unaffected when in power-down. The time to exit
power-down is typically 2.5
μ
s for V
DD
= 5 V and 5
μ
s when
V
DD
= 3 V. This is the time from the falling edge of the sixteenth
SCLK pulse to when the output voltage deviates from its power-
down voltage. See Figure 21 for a plot.
AMPLIFIER
POWER-DOWN
CIRCUITRY
RESISTOR
STRING DAC
V
OUT
Figure 32. Output Stage During Power-Down
MICROPROCESSOR INTERFACING
AD5304/AD5314/AD5324 to ADSP-2101/ADSP-2103 Interface
Figure 33 shows a serial interface between the AD5304/AD5314/
AD5324 and the ADSP-2101/ADSP-2103. The ADSP-2101/
ADSP-2103 should be set up to operate in the SPORT Transmit
Alternate Framing Mode. The ADSP-2101/ADSP-2103 SPORT
is programmed through the SPORT control register and should
be configured as follows: Internal Clock Operation, Active-Low
Framing, 16-Bit Word Length. Transmission is initiated by writing
a word to the Tx register after the SPORT has been enabled.
The data is clocked out on each rising edge of the DSP’s serial
clock and clocked into the AD5304/AD5314/AD5324 on the
falling edge of the DAC’s SCLK.
AD5304/
AD5314/
AD5324*
SCLK
DIN
SYNC
TFS
DT
SCLK
ADSP-2101/
ADSP-2103*
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 33. AD5304/AD5314/AD5324 to ADSP-2101/
ADSP-2103 Interface
AD5304/AD5314/AD5324 to 68HC11/68L11 Interface
Figure 34 shows a serial interface between the AD5304/AD5314/
AD5324 and the 68HC11/68L11 microcontroller. SCK of the
68HC11/68L11 drives the SCLK of the AD5304/AD5314/
AD5324, while the MOSI output drives the serial data line (DIN)
of the DAC. The
SYNC
signal is derived from a port line (PC7).
The setup conditions for correct operation of this interface are
as follows: the 68HC11/68L11 should be configured so that its
CPOL bit is a 0 and its CPHA bit is a 1. When data is being
transmitted to the DAC, the
SYNC
line is taken low (PC7).
When the 68HC11/68L11 is configured as above, data appearing
on the MOSI output is valid on the falling edge of SCK. Serial
data from the 68HC11/68L11 is transmitted in 8-bit bytes with
only eight falling clock edges occurring in the transmit cycle. Data
is transmitted MSB first. In order to load data to the AD5304/
AD5314/AD5324, PC7 is left low after the first eight bits are
transferred, a second serial write operation is performed to the
DAC, and PC7 is taken high at the end of this procedure.
DIN
SCLK
SYNC
PC7
SCK
MOSI
68HC11/68L11*
*ADDITIONAL PINS OMITTED FOR CLARITY.
AD5304/
AD5314/
AD5324*
Figure 34. AD5304/AD5314/AD5324 to 68HC11/68L11
Interface
AD5304/AD5314/AD5324 to 80C51/80L51 Interface
Figure 35 shows a serial interface between the AD5304/AD5314/
AD5324 and the 80C51/80L51 microcontroller. The setup for
the interface is as follows: TxD of the 80C51/80L51 drives SCLK
of the AD5304/AD5314/AD5324, while RxD drives the serial
data line of the part. The
SYNC
signal is again derived from a
bit-programmable pin on the port. In this case port line P3.3 is
used. When data is to be transmitted to the AD5304/AD5314/
AD5324, P3.3 is taken low. The 80C51/80L51 transmits data
only in 8-bit bytes; thus only eight falling clock edges occur in
the transmit cycle. To load data to the DAC, P3.3 is left low
after the first eight bits are transmitted, and a second write cycle
is initiated to transmit the second byte of data. P3.3 is taken high
following the completion of this cycle. The 80C51/80L51 outputs
the serial data in a format which has the LSB first. The AD5304/
AD5314/AD5324 requires its data with the MSB as the first bit
received. The 80C51/80L51 transmit routine should take this
into account.
DIN
SCLK
SYNC
P3.3
TxD
RxD
80C51/80L51*
*ADDITIONAL PINS OMITTED FOR CLARITY.
AD5304/
AD5314/
AD5324*
Figure 35. AD5304/AD5314/AD5324 to 80C51/80L51
Interface
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