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参数资料
| 型号： | AD5322BRM |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | DAC |
| 英文描述： | 12-bit, 210MSPS ADC with DDR LVDS/CMOS outputs 48-VQFN -40 to 85 |
| 中文描述： | SERIAL INPUT LOADING, 8 us SETTLING TIME, 12-BIT DAC, PDSO10 |
| 封装： | MO-187BA, MSOP-10 |
| 文件页数： | 15/16页 |
| 文件大小： | 207K |
| 代理商： | AD5322BRM |
REV. 0
AD5302/AD5312/AD5322
–15–
Decoding Multiple AD5302/AD5312/AD5322s
The
SYNC
pin on the AD5302/AD5312/AD5322 can be used
in applications to decode a number of DACs. In this applica-
tion, all the DACs in the system receive the same serial clock
and serial data, but only the
SYNC
to one of the devices will be
active at any one time allowing access to two channels in this
eight-channel system. The 74HC139 is used as a 2-to-4 line
decoder to address any of the DACs in the system. To prevent
timing errors from occurring, the enable input should be brought
to its inactive state while the coded address inputs are changing
state. Figure 40 shows a diagram of a typical setup for decoding
multiple AD5302/AD5312/AD5322 devices in a system.
74HC139
V
CC
V
DD
ENABLE
CODED
ADDRESS
1G
1A
1B
DGND
1Y0
1Y1
1Y2
1Y3
SCLK
DIN
AD5302/AD5312/AD5322
SYNC
DIN
SCLK
SYNC
DIN
SCLK
SYNC
DIN
SCLK
SYNC
DIN
SCLK
AD5302/AD5312/AD5322
AD5302/AD5312/AD5322
AD5302/AD5312/AD5322
Figure 40. Decoding Multiple AD5302/AD5312/AD5322
Devices in a System
AD5302/AD5312/AD5322 as a Digitally Programmable
Window Detector
A digitally programmable upper/lower limit detector using the
two DACs in the AD5302/AD5312/AD5322 is shown in Figure
41. The upper and lower limits for the test are loaded to DACs
A and B which, in turn, set the limits on the CMP04. If the
signal at the V
IN
input is not within the programmed window,
an LED will indicate the fail condition.
AD5302/AD5312/
AD5322
SYNC
V
REF
A
V
REF
B
SCLK
DIN
V
DD
GND
V
OUT
A
V
OUT
B
+5V
0.1
m
F
10
m
F
SCLK
DIN
SYNC
V
REF
V
IN
1/2
CMP04
1k
V
FAIL
PASS/
FAIL
1k
V
PASS
1/6 74HC05
Figure 41. Window Detector Using AD5302/AD5312/AD5322
Coarse and Fine Adjustment Using the AD5302/AD5312/
AD5322
The DACs in the AD5302/AD5312/AD5322 can be paired
together to form a coarse and fine adjustment function, as
shown in Figure 42. DAC A is used to provide the coarse ad-
justment while DAC B provides the fine adjustment. Varying
the ratio of R1 and R2 will change the relative effect of the
coarse and fine adjustments. With the resistor values and exter-
nal reference shown, the output amplifier has unity gain for the
DAC A output, so the output range is 0 V to 2.5 V – 1 LSB. For
DAC B the amplifier has a gain of 7.6
×
10
–3
, giving DAC B a
range equal to 19 mV.
The circuit is shown with a 2.5 V reference, but reference volt-
ages up to V
DD
may be used. The op amps indicated will allow a
rail-to-rail output swing.
1
m
F
V
REF
A
AD5302/AD5312/
AD5322
V
DD
GND
V
OUT
B
0.1
m
F
10
m
F
V
DD
= +5V
V
OUT
V
IN
GND
EXT
REF
AD820/
OP295
+5V
R3
51.2k
V
R4
390
V
AD780/REF192
WITH V
DD
= +5V
V
OUT
A
V
REF
B
R1
390
V
R2
51.2k
V
V
OUT
Figure 42. Coarse/Fine Adjustment
Power Supply Bypassing and Grounding
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD5302/AD5312/AD5322 is mounted should be designed so
that the analog and digital sections are separated, and confined
to certain areas of the board. If the AD5302/AD5312/AD5322
is in a system where multiple devices require an AGND-to-DGND
connection, the connection should be made at one point only.
The star ground point should be established as close as possible
to the AD5302/AD5312/AD5322. The AD5302/AD5312/
AD5322 should have ample supply bypassing of 10
μ
F in paral-
lel with 0.1
μ
F on the supply located as close to the package as
possible, ideally right up against the device. The 10
μ
F capaci-
tors are the tantalum bead type. The 0.1
μ
F capacitor should
have low Effective Series Resistance (ESR) and Effective Series
Inductance (ESI), like the common ceramic types that provide a
low impedance path to ground at high frequencies to handle
transient currents due to internal logic switching.
The power supply lines of the AD5302/AD5312/AD5322 should
use as large a trace as possible to provide low impedance paths
and reduce the effects of glitches on the power supply line. Fast
switching signals such as clocks should be shielded with digital
ground to avoid radiating noise to other parts of the board, and
should never be run near the reference inputs. Avoid crossover
of digital and analog signals. Traces on opposite sides of the
board should run at right angles to each other. This reduces the
effects of feedthrough through the board. A microstrip tech-
nique is by far the best, but not always possible with a double-
sided board. In this technique, the component side of the board
is dedicated to ground plane while signal traces are placed on
the solder side.
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