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参数资料
| 型号： | AD53500 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Dual Channel 11-Bits, 125 MSPS ADC With Parallel CMOS/DDR LVDS Outputs 64-VQFN -40 to 85 |
| 中文描述： | 高速，高电流能力管脚驱动 |
| 文件页数： | 2/7页 |
| 文件大小： | 101K |
| 代理商： | AD53500 |
–2–
REV. 0
AD53500–SPECIFICATIONS
(All specifications are at T
J
= +85
8
C
6
5
8
C, +V
S
= +10 V
6
3%, –V
S
= +6 V
6
3%
unless otherwise noted. All temperature coefficients are measured over T
J
= 75
8
C–95
8
C). (In test figures, voltmeter loading is 1 M
V
or greater,
scope probe loading is 100 k
V
in parallel with 5 pF.) 39 nF capacitors must be connected between V
CC
and V
HDCPL
and between V
EE
and V
LDCPL
.
Parameter
Min
Typ
Max
Units
Test Conditions
DIFFERENTIAL INPUT CHARACTERISTICS
(DATA to
DATA
, INH to
INH
)
Common-Mode Input Voltage
Differential Input Range
Bias Current
–2
+5
Volts
ECL or TTL
±
100
ECL = –0.8 V/–1.8 V, TTL = 0 V/5 V
V
CM
= –2 V, +5 V
μ
A
REFERENCE INPUTS
Bias Currents
–50
+50
μ
A
V
L
, V
H
= 5 V
OUTPUT CHARACTERISTICS
Logic High Range
Logic Low Range
Amplitude (V
H
and V
L
)
+1
–2
0.1
+6
+2
8
Volts
Volts
Volts
DATA = H, V
L
= –2 V, V
H
= +1 V to +6 V
DATA = L, V
L
= –2 V to +2 V, V
H
= +6 V
V
L
= –0.05 V, V
H
= +0.05 V and
V
L
= –2 V, V
H
= +6 V
100 mV Output Amplitude
V
H
, V
L
Interaction
Absolute Accuracy
V
H
Offset
V
H
Gain + Linearity Error
V
L
Offset
V
L
Gain + Linearity Error
Offset TC, V
H
or V
L
Output Resistance
–10
+10
mV
–100
+100
mV
% of V
H
+ mV
mV
% of V
L
+ mV
mV/
°
C
DATA = H, V
H
= 0 V, V
L
= –2 V
DATA = H, V
L
= –2 V, V
H
= +1 V to +6 V
DATA = L, V
L
= 0 V, V
H
= +6 V
DATA = L, V
L
= –2 V to +2 V, V
H
= +6 V
V
L
, V
H
= 0 V, +5 V and –2 V, 0 V
V
H
= +3 V, V
L
= 0 V, I
OUT
= 0, –30 mA,
+30 mA
C
BYP
= 39 nF, V
H
= +5 V, V
L
= 0 V
C
LOAD
= 1000 pF, Tr/Tf = 10 ns
Output to –2 V, V
H
= +6 V, V
L
= –1 V,
DATA = H and Output to +6 V, V
H
= +6 V,
V
L
= –2 V, DATA = L
±
0.3
±
5
–100
+100
±
0.3
±
5
0.5
2.5
1.5
5.5
Dynamic Current Limit
400
mA
Static Current Limit
60
–180
180
–60
mA
mA
DYNAMIC PERFORMANCE, DRIVE
(V
H
and V
L
)
Propagation Delay Time
2.5
ns
Measured at 50%, V
H
= +400 mV,
V
L
= –400 mV
Measured at 50%, V
H
= +400 mV,
V
L
= –400 mV
Measured at 50%, V
H
= +400 mV,
V
L
= –400 mV
Propagation Delay TC
1
ps/
°
C
Delay Matching, Edge-to-Edge
100
ps
Rise and Fall Time
1 V Swing
3 V Swing
5 V Swing
Rise and Fall Time TC
1 V Swing
3 V Swing
5 V Swing
Overshoot, Undershoot and Preshoot
Settling Time
to 15 mV
to 4 mV
Delay Change vs. Pulsewidth
0.85
2.5
4.0
ns
ns
ns
Measured 20%–80%, V
L
= 0 V, V
H
= 1 V
Measured 10%–90%, V
L
= 0 V, V
H
= 3 V
Measured 10%–90%, V
L
= 2 V, V
H
= 3 V
±
1
±
2
±
3
+5.0 +30
ps/
°
C
ps/
°
C
ps/
°
C
% of Step + mV
Measured 20%–80%, V
L
= 0 V, V
H
= 1 V
Measured 10%–90%, V
L
= 0 V, V
H
= 3 V
Measured 10%–90%, V
L
= 0 V, V
H
= 5 V
V
H
–V
L
= 0.5 V, 1 V, 3 V, 8 V
40
8
100
ns
μ
s
ps
V
L
= 0 V, V
H
= 0.5 V
V
L
= 0 V, V
H
= 0.5 V
V
L
= 0 V, V
H
= 2 V, Pulsewidth = 2.5 ns/
Period = 10 ns and Pulsewidth = 30 ns/
Period = 120 ns
Minimum Pulsewidth
3 V Swing
3.8
ns
V
L
= 0 V, V
H
= 3 V, Output = 2.7 V p-p,
Measure at 50%
V
L
= 0 V, V
H
= 5 V, Output = 4.5 V p-p,
Measure at 50%
V
L
= –1.8 V, V
H
= –0.8 V, V
OUT
> 600 mV p-p
5 V Swing
5.5
ns
Toggle Rate
300
MHz
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