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参数资料
| 型号： | AD53508 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | PPMU Circuit |
| 中文描述： | PPMU电路 |
| 文件页数： | 5/8页 |
| 文件大小： | 125K |
| 代理商： | AD53508 |
AD53508
–5–
REV. 0
Table I. Data Table
Data Latch Bits
S1
S13,
S10
S15,
S14
S2
S3
S4
S5
S6
S7
S9
S17
S8
S16
S11
S12
S18
Voltage Force/Current Measure
Irange 0
On
Off
Irange 1
On
Off
Integrate Range
On
Off
Integrate
On
Off
Hold/Measure
On
Off
Current Force/Voltage Measure
Irange 0
On
On
Irange 1
On
On
Disable Mode: Output Connected
X
X
Verify/Voltage Force
On
On
Verify/Current Force
On
Off
Disconnect
X
X
DAC2 Select: Enabled
X
X
On
On
Off
On
Off
Off
Off
On
On
On
Off
Off
Off
On
On
On
Off
On
Off
Off
Off
On
On
Off
On
Off
Off
On
On
On
Off
On
Off
Off
Off
On
On
Off
Off
On
On
On
On
On
Off
On
Off
Off
Off
On
Off
Off
Off
On
On
On
On
On
Off
On
Off
On
On
Off
Off
Off
Off
Off
On
On
Off
Off
On
On
Off
Off
Off
On
On
On
Off
Off
Off
On
Off
Off
On
On
Off
Off
Off
On
On
Off
On
Off
Off
On
X
On
Off
Off
On
Off
Off
On
X
On
Off
Off
Off
On
Off
On
Off
On
Off
Off
Off
On
On
On
Off
Off
Off
On
On
Off
On
On
Off
Off
Off
On
On
On
Off
Off
Off
On
X
On
Off
X
X
On
Off
Off
On
Off
Off
Off
On
Off
X
X
X
Off
On
X
X
X
X
X
X
X
X
X
CAPACITOR
CHARGE
INTEGRATE*
HOLD*
INTEGRATE
HOLD
DISCHARGE
CAPACITOR
* = ACTIVE LO
Figure 1. Integrate/Current Measure Timing Diagram
Table II. Truth Table
* = Active LO
FV/MI 2 mA
FV/MI 200 mA
FV/MI Integrate DAC1
FV/MI Integrate DAC 2
FI/MV 2 mA
FI/MV 200
μ
A
FV/Verify
FI/Verify
Disconnect
Disable
Control
Input
Voltage
Settle
Inte-
grate
Voltage
Settle
Inte-
grate
Output
Connected
DAC1
DAC2
DAC1
DAC2
Hold
Hold
DAC1
DAC2
DAC1
DAC2
DAC1
DAC2
DAC1
DAC2
M_CON*
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
X
X
VERIFY*
HI
HI
HI
HI
HI
HI
HI
HI
HI
HI
HI
HI
HI
HI
LO
LO
LO
LO
X
X
FORCE_I*
HI
HI
HI
HI
HI
HI
HI
HI
HI
HI
LO
LO
LO
LO
HI
HI
LO
LO
X
X
FORCE_EN*
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
X
HI
DAC1_SEL*
LO
HI
LO
HI
LO
LO
LO
HI
HI
HI
LO
HI
LO
HI
LO
HI
LO
HI
X
X
INTEG*
HI
HI
HI
HI
HI
LO
LO
HI
LO
LO
HI
HI
HI
HI
HI
HI
HI
HI
X
X
HOLD*
HI
HI
HI
HI
HI
HI
LO
HI
HI
LO
HI
HI
HI
HI
HI
HI
HI
HI
X
X
I_RANGE0*
LO
LO
HI
HI
HI
HI
HI
HI
HI
HI
LO
LO
HI
HI
X
X
X
X
X
X
I_RANGE1*
HI
HI
LO
LO
HI
HI
HI
HI
HI
HI
HI
HI
LO
LO
X
X
X
X
X
X
OUTPUT_CON*
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
HI
LO
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