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参数资料
| 型号： | AD5382 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | 32-Channel, 3 V/5 V, Single-Supply, 14-Bit, Voltage Output DAC |
| 中文描述： | 32通道，3伏/ 5 V，单电源，14位，电压输出DAC |
| 文件页数： | 21/40页 |
| 文件大小： | 616K |
| 代理商： | AD5382 |
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AD5382
FUNCTIONAL DESCRIPTION
DAC ARCHITECTURE—GENERAL
The AD5382 is a complete, single-supply, 32-channel voltage
output DAC that offers 14-bit resolution. The part is available in
a 100-lead LQFP package and features both a parallel and a
serial interface. This product includes an internal, software
selectable, 1.25 V/2.5 V, 10 ppm/°C reference that can be used to
drive the buffered reference inputs; alternatively, an external
reference can be used to drive these inputs. Internal/external
reference selection is via the CR10 bit in the control register;
CR12 selects the reference magnitude if the internal reference is
selected. All channels have an on-chip output amplifier with
rail-to-rail output capable of driving 5 k in parallel with a
200 pF load.
Rev. 0 | Page 21 of 40
0
V
OUT
R
R
14-BIT
DAC
DAC
REG
m REG
c REG
×1 INPUT
REG
×2
INPUT DATA
V
REF
AVDD
Figure 27. Single-Channel Architecture
The architecture of a single DAC channel consists of a 14-bit
resistor-string DAC followed by an output buffer amplifier
operating at a gain of 2. This resistor-string architecture
guarantees DAC monotonicity. The 14-bit binary digital code
loaded to the DAC register determines at what node on the
string the voltage is tapped off before being fed to the output
amplifier. Each channel on these devices contains independent
offset and gain control registers that allow the user to digitally
trim offset and gain. These registers give the user the ability to
calibrate out errors in the complete signal chain, including the
DAC, using the internal m and c registers, which hold the
correction factors. All channels are double buffered, allowing
synchronous updating of all channels using the LDAC pin.
Figure 27 shows a block diagram of a single channel on the
AD5382. The digital input transfer function for each DAC can
be represented as
x2
= [(
m
+ 2)/ 2
n
×
x1
] + (
c
– 2
n
– 1
)
where:
x2
is the data-word loaded to the resistor string DAC.
x1
is the 14-bit data-word written to the DAC input register.
m
is the gain coefficient (default is 0x3FFE on the AD5382).
The gain coefficient is written to the 13 most significant bits
(DB13 to DB1) and LSB (DB0) is a zero.
n
= DAC resolution (
n
= 14 for AD5382).
c
is the14-bit offset coefficient (default is 0x2000).
The complete transfer function for these devices can be
represented as
V
OUT
= 2 ×
V
REF
×
x2
/2
n
x2
is the data-word loaded to the resistor string DAC.
V
REF
is the
internal reference voltage or the reference voltage externally
applied to the DAC REFOUT/REFIN pin. For specified
performance, an external reference voltage of 2.5 V is
recommended for the AD5380-5, and 1.25 V for the AD5380-3.
DATA DECODING
The AD5382 contains a 14-bit data bus, DB13–DB0. Depending
on the value of REG1 and REG0 (see Table 11), this data is
loaded into the addressed DAC input registers, offset (c)
registers, or gain (m) registers. The format data, offset (c), and
gain (m) register contents are shown in Table 12 to Table 14.
Table 11. Register Selection
REG1
REG0
Register Selected
1
1
Input Data Register (x1)
1
0
Offset Register (c)
0
1
Gain Register (m)
0
0
Special Function Registers (SFRs)
Table 12. DAC Data Format (REG1 = 1, REG0 = 1)
DB13 to DB0
11
1111
1111
1111
11
1111
1111
1110
10
0000
0000
0001
10
0000
0000
0000
01
1111
1111
1111
00
0000
0000
0001
00
0000
0000
0000
DAC Output (V)
2 V
REF
× (16383/16384)
2 V
REF
× (16382/16384)
2 V
REF
× (8193/16384)
2 V
REF
× (8192/16384)
2 V
REF
× (8191/16384)
2 V
REF
× (1/16384)
0
Table 13. Offset Data Format (REG1 = 1, REG0 = 0)
DB13 to DB0
11
1111
1111
1111
11
1111
1111
1110
10
0000
0000
0001
10
0000
0000
0000
01
1111
1111
1111
00
0000
0000
0001
00
0000
0000
0000
Offset (LSB)
+8191
+8190
+1
0
–1
–8191
–8192
Table 14. Gain Data Format (REG1 = 0, REG0 = 1)
DB13 to DB0
11
1111
1111
10
1111
1111
01
1111
1111
00
0111
1111
00
0000
0000
Gain Factor
1
0.75
0.5
0.25
0
1110
1110
1110
1110
0000
相关PDF资料 |
PDF描述 |
|---|---|
| AD5382BST-3 | 32-Channel, 3 V/5 V, Single-Supply, 14-Bit, Voltage Output DAC |
| AD5382BST-5 | 32-Channel, 3 V/5 V, Single-Supply, 14-Bit, Voltage Output DAC |
| AD5382BST-5-REEL | 32-Channel, 3 V/5 V, Single-Supply, 14-Bit, Voltage Output DAC |
| AD5383BST-3 | 32-Channel, 3 V/5 V, Single-Supply, 14-Bit, Voltage Output DAC |
| AD5383BST-5 | 32-Channel, 3 V/5 V, Single-Supply, 14-Bit, Voltage Output DAC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD5382BST-3 | 制造商:Analog Devices 功能描述:DAC 32-CH Resistor-String 14-bit 100-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:32/40-CHANNEL 3V/5V SINGLE SUPPLY 12/14-BIT VOUT DAC - Bulk |
| AD5382BST-3-REEL | 制造商:Analog Devices 功能描述:DAC 32-CH Resistor-String 14-bit 100-Pin LQFP T/R |
| AD5382BST-5 | 制造商:Analog Devices 功能描述:DAC 32-CH Resistor-String 14-bit 100-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:32-CHN 5V SINGLE SUPPLY 14-BIT VOUT I.C. - Bulk |
| AD5382BST-5-REEL | 制造商:Analog Devices 功能描述:DAC 32-CH Resistor-String 14-bit 100-Pin LQFP T/R |
| AD5382BSTZ-3 | 功能描述:IC DAC 14BIT 32CHAN 3V 100LQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1,000 系列:- 设置时间:1µs 位数:8 数据接口:串行 转换器数目:8 电压电源:双 ± 功率耗散（最大）:941mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC W 包装:带卷 (TR) 输出数目和类型:8 电压，单极 采样率（每秒）:* |
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