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参数资料
| 型号： | AD5382 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | 32-Channel, 3 V/5 V, Single-Supply, 14-Bit, Voltage Output DAC |
| 中文描述： | 32通道，3伏/ 5 V，单电源，14位，电压输出DAC |
| 文件页数： | 27/40页 |
| 文件大小： | 616K |
| 代理商： | AD5382 |
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AD5382
Daisy-Chain Mode
For systems that contain several devices, the SDO pin may be
used to daisy-chain several devices together. This daisy-chain
mode can be useful in system diagnostics and in reducing the
number of serial interface lines.
Rev. 0 | Page 27 of 40
By connecting the DCEN (Daisy-Chain Enable) pin high, daisy-
chain mode is enabled. The first falling edge of SYNC starts the
write cycle. The SCLK is continuously applied to the input shift
register when SYNC is low. If more than 24 clock pulses are
applied, the data ripples out of the shift register and appears on
the SDO line. This data is clocked out on the rising edge of
SCLK and is valid on the falling edge. By connecting the SDO of
the first device to the DIN input on the next device in the chain,
a multidevice interface is constructed. Twenty-four clock pulses
are required for each device in the system. Therefore, the total
number of clock cycles must equal 24N, where N is the total
number of AD538x devices in the chain.
When the serial transfer to all devices is complete, SYNC is
taken high. This latches the input data in each device in the
daisy-chain and prevents any further data from being clocked
into the input shift register.
If the SYNC is taken high before 24 clocks are clocked into the
part, this is considered a bad frame and the data is discarded.
The serial clock may be either a continuous or a gated clock. A
continuous SCLK source can only be used if it can be arranged
that SYNC is held low for the correct number of clock cycles. In
gated clock mode, a burst clock containing the exact number of
clock cycles must be used and SYNC must be taken high after
the final clock to latch the data.
Readback Mode
Readback mode is invoked by setting the R/W bit = 1 in the
serial input register write. With R/W = 1, Bits A4 to A0, in
association with Bits REG1 and REG0, select the register to be
read. The remaining data bits in the write sequence are don’t
cares. During the next SPI write, the data appearing on the SDO
output will contain the data from the previously addressed
register. For a read of a single register, the NOP command can
be used in clocking out the data from the selected register on
SDO. Figure 30 shows the readback sequence. For example, to
read back the M register of channel 0 on the AD5382, the
following sequence should be implemented. First, write
0x404XXX to the AD5382 input register. This configures the
AD5382 for read mode with the m register of Channel 0
selected. Note that data bits DB13 to DB0 are don’t cares. Follow
this with a second write, a NOP condition, 0x000000. During
this write, the data from the m register is clocked out on the
DOUT line, i.e., data clocked out will contain the data from the
m register in Bits DB13 to DB0, and the top 10 bits contain the
address information as previously written. In readback mode,
the SYNC signal must frame the data. Data is clocked out on the
rising edge of SCLK and is valid on the falling edge of the SCLK
signal. If the SCLK idles high between the write and read
operations of a readback operation, the first bit of data is
clocked out on the falling edge of SYNC.
0
24
48
SCLK
SYNC
DIN
SDO
UNDEFINED
SELECTED REGISTER DATA CLOCKED OUT
NOP CONDITION
INPUT WORD SPECIFIES REGISTER TO BE READ
DB23
DB0
DB0
DB23
DB23
DB0
DB0
DB23
Figure 30. Serial Readback Operation
相关PDF资料 |
PDF描述 |
|---|---|
| AD5382BST-3 | 32-Channel, 3 V/5 V, Single-Supply, 14-Bit, Voltage Output DAC |
| AD5382BST-5 | 32-Channel, 3 V/5 V, Single-Supply, 14-Bit, Voltage Output DAC |
| AD5382BST-5-REEL | 32-Channel, 3 V/5 V, Single-Supply, 14-Bit, Voltage Output DAC |
| AD5383BST-3 | 32-Channel, 3 V/5 V, Single-Supply, 14-Bit, Voltage Output DAC |
| AD5383BST-5 | 32-Channel, 3 V/5 V, Single-Supply, 14-Bit, Voltage Output DAC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD5382BST-3 | 制造商:Analog Devices 功能描述:DAC 32-CH Resistor-String 14-bit 100-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:32/40-CHANNEL 3V/5V SINGLE SUPPLY 12/14-BIT VOUT DAC - Bulk |
| AD5382BST-3-REEL | 制造商:Analog Devices 功能描述:DAC 32-CH Resistor-String 14-bit 100-Pin LQFP T/R |
| AD5382BST-5 | 制造商:Analog Devices 功能描述:DAC 32-CH Resistor-String 14-bit 100-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:32-CHN 5V SINGLE SUPPLY 14-BIT VOUT I.C. - Bulk |
| AD5382BST-5-REEL | 制造商:Analog Devices 功能描述:DAC 32-CH Resistor-String 14-bit 100-Pin LQFP T/R |
| AD5382BSTZ-3 | 功能描述:IC DAC 14BIT 32CHAN 3V 100LQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1,000 系列:- 设置时间:1µs 位数:8 数据接口:串行 转换器数目:8 电压电源:双 ± 功率耗散（最大）:941mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC W 包装:带卷 (TR) 输出数目和类型:8 电压，单极 采样率（每秒）:* |
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