参数资料
型号: AD5541LRZ
厂商: Analog Devices Inc
文件页数: 7/20页
文件大小: 0K
描述: IC DAC 16BIT SERIAL IN 8-SOIC
产品培训模块: Data Converter Fundamentals
DAC Architectures
设计资源: How to Achieve High Precision Voltage Level Setting Using AD5541A/42A (CN0169)
标准包装: 1
设置时间: 1µs
位数: 16
数据接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
电压电源: 单电源
功率耗散(最大): 825µW
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SO
包装: 管件
输出数目和类型: 1 电压,单极;1 电压,双极
采样率(每秒): 1.5M
产品目录页面: 783 (CN2011-ZH PDF)
Data Sheet
AD5541/AD5542
Rev. F | Page 15 of 20
APPLICATIONS INFORMATION
OPTOCOUPLER INTERFACE
The digital inputs of the AD5541/AD5542 are Schmitt-triggered so
that they can accept slow transitions on the digital input lines.
This makes these parts ideal for industrial applications where it
may be necessary to isolate the DAC from the controller via
optocouplers. Figure 29 illustrates such an interface.
10k
10F
0.1F
VDD
VOUT
VDD
SCLK
POWER
10k
VDD
CS
DIN
GND
SCLK
10k
VDD
DIN
5V
REGULATOR
AD5541/AD5542
07557-
029
Figure 29. AD5541/AD5542 in an Optocoupler Interface
DECODING MULTIPLE AD5541/AD5542s
The CS pin of the AD5541/AD5542 can be used to select one of
a number of DACs. All devices receive the same serial clock and
serial data, but only one device receives the CS signal at any one
time. The DAC addressed is determined by the decoder. There is
some digital feedthrough from the digital input lines. Using a
burst clock minimizes the effects of digital feedthrough on the
analog signal channels. Figure 30 shows a typical circuit.
AD5541/AD5542
CS
DIN
SCLK
VOUT
AD5541/AD5542
CS
DIN
SCLK
VOUT
AD5541/AD5542
CS
DIN
SCLK
VOUT
AD5541/AD5542
CS
DIN
SCLK
VOUT
VDD
DGND
EN
CODED
ADDRESS
SCLK
DIN
ENABLE
DECODER
07557-
030
Figure 30. Addressing Multiple AD5541/AD5542s
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