参数资料
型号: AD5583YRVZ
厂商: Analog Devices Inc
文件页数: 7/20页
文件大小: 0K
描述: IC DAC 10BIT QUAD VOUT 48-TSSOP
产品培训模块: Data Converter Fundamentals
DAC Architectures
标准包装: 39
设置时间: 5µs
位数: 10
数据接口: 并联
转换器数目: 4
电压电源: 模拟和数字,双 ±
功率耗散(最大): 30mW
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 48-TFSOP(0.240",6.10mm 宽)
供应商设备封装: 48-TSSOP
包装: 管件
输出数目和类型: 4 电压,单极;4 电压,双极
采样率(每秒): 200k
产品目录页面: 783 (CN2011-ZH PDF)
REV. A
AD5582/AD5583
–15–
FFFH
100
1k
10k
100k
1M
10M
800H
001H
000H
400H
200H
100H
080H
040H
020H
010H
008H
004H
002H
FREQUENCY (Hz)
A
TTENU
A
TION
(dB)
–96
–72
–48
–24
0
TPC 25. AD5582 Multiplying Bandwidth
Test Circuit
DAC
CL
VOUT
1k
VDD
Test Circuit 1
HOURS OF OPERATION AT 150 C
0.8
0
100
600
ERR
OR
(LSB)
–0.8
0
300
–0.6
0.4
–0.4
200
0.6
–0.2
0.2
VDD = +5V
VSS = –5V
VREFH = +4V
VREFL = –4V
400
500
+3
–3
+3
–3
GE DRIFT
ZSE DRIFT
TPC 26. AD5582 Long-Term Drift
THEORY OF OPERATION
The AD5582/AD5583 are quad, voltage output, 12-/10-bit parallel
input DACs in compact TSSOP-48 packages.
Each DAC is a voltage switching, high impedance (R = 20 k
W),
R-2R ladder configuration with segmentation to optimize die
area and precision. Figure 3 shows a simplified R-2R structure
without the segmentation. The 2R resistances are switched
between VREFH and VREFL, and the output is obtained from
the rightmost ladder node. As the code is sequenced through
all possible states, the voltage of this node changes in steps of
(2/3 VREFH – VREFL)/(2
N – 1) starting from the lowest V
REFL and
going to the highest VREFH – DUTLSB. Buffering it with an
amplifier with a gain of 1.5 brings the output to:
V
D
VV
V
OUT
N
REFH
REFL
=
()+()
21
(1)
where D is the decimal equivalent of the data bits and N is the
numbers of bits.
If –VREFL is equal to VREFH as VREF, VOUT is simplified to:
V
D
V
OUT
REF
=
2
4095
1
(For AD5582) (2)
V
D
V
OUT
REF
=
2
1023
1
(For AD5583) (3)
The advantage of this scheme is that it allows the DAC to inter-
polate between two voltages for differential references or
single-ended reference.
These DACs feature double buffers, which allow both synchro-
nous and asynchronous channels update with additional data
readback capability. These parts can be reset to zero scale or mid-
scale controlled by the
RS and MSB pins. When RS is activated,
the MSB of 0 resets the DACs to zero scale and the MSB of 1
resets the DACs to midscale. The ability to operate from wide
supply voltages, +5 V to +15 V or
±5 V, with multiplying bipolar
references is another key feature of these DACs.
+
VO
R
2R
SW0
b0
2R
SW1
b1
2R
SW2
b2
2R
SWn–3
bn–2
2R
SWn–1
bn–1
2R
R
VREFL +
VREFH
+
Figure 3. Simplified R-2R Architecture
(Segmentation Not Shown)
Power Supplies
There are three separate power supplies needed for the opera-
tion of the DACs. For dual supply, VSS can be set from –6.5 V
to –2.7 V and VDD can be set from +2.7 V to +6.5 V. For single
supply, VSS should be set at 0 V while VDD is set from 3 V to
16.5 V. However, setting the single supply of VDD below 4.5 V
can impact the overall accuracy of the device.
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