参数资料
| 型号： | AD5621ACPZ-RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 6/24页 |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT SPI 6LFCSP |
| 标准包装： | 3,000 |
| 系列： | nanoDAC™ |
| 设置时间： | 6µs |
| 位数： | 12 |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 500µW |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 6-WDFN 裸露焊盘 |
| 供应商设备封装： | 6-LFCSP-WD（2x3） |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 1 电压，单极；1 电压，双极 |
AD5601/AD5611/AD5621
Data Sheet
Rev. G | Page 14 of 24
THEORY OF OPERATION
DAC SECTION
The AD5601/AD5611/AD5621 DACs are fabricated on a
CMOS process. The architecture consists of a string DAC
followed by an output buffer amplifier. Figure 39 is a block
diagram of the DAC architecture.
Figure 39. DAC Architecture
Because the input coding to the DAC is straight binary, the ideal
output voltage is given by
×
=
n
DD
OUT
D
V
2
where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register.
n is the bit resolution of the DAC.
RESISTOR STRING
The resistor string structure is shown in Figure 40. It is simply a
string of resistors, each of Value R. The code loaded to the DAC
register determines at which node on the string the voltage is
tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string
to the amplifier. Because it is a string of resistors, it is guaran-
teed monotonic.
Figure 40. Resistor String Structure
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating rail-to-rail
voltages on its output, giving an output range of 0 V to VDD. It is
capable of driving a load of 2 k in parallel with 1000 pF to
GND. The source and sink capabilities of the output amplifier
are shown in Figure 25. The slew rate is 0.5 V/s, with a half-
scale settling time of 8 s with the output loaded.
SERIAL INTERFACE
The AD5601/AD5611/AD5621 have a 3-wire serial interface
(SYNC, SCLK, and SDIN) that is compatible with SPI, QSPI,
and MICROWIRE interface standards as well as most DSPs. See
Figure 2 for a timing diagram of a typical write sequence.
The write sequence begins by bringing the SYNC line low. Data
from the SDIN line is clocked into the 16-bit shift register on
the falling edge of SCLK. The serial clock frequency can be as
high as 30 MHz, making the AD5601/AD5611/AD5621 com-
patible with high speed DSPs. On the 16th falling clock edge,
the last data bit is clocked in and the programmed function is
executed (a change in DAC register contents and/or a change
in the mode of operation). At this stage, the SYNC line may be
kept low or brought high. In either case, it must be brought high
for a minimum of 33 ns before the next write sequence so that a
falling edge of SYNC can initiate the next write sequence.
Because the SYNC buffer draws more current when VIN = 1.8 V
than it does when VIN = 0.8 V, SYNC should be idled low
between write sequences for even lower power operation of the
part, as mentioned previously. However, it must be brought
high again just before the next write sequence.
INPUT SHIFT REGISTER
The input shift register is 16 bits wide (see Figure 41). The first
two bits are control bits, which control the operating mode of
the part (normal mode or any one of three power-down
modes). For a complete description of the various modes, see
the Power-Down Modes section. For the AD5621, the next
12 bits are the data bits, which are transferred to the DAC
register on the 16th falling edge of SCLK. The information in
the last two bits is ignored by the AD5621. See Figure 42 and
Figure 43 for the AD5611 and AD5601 input shift register map.
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept low for at
least 16 falling edges of SCLK and the DAC is updated on the
16th falling edge. However, if SYNC is brought high before the
16th falling edge, this acts as an interrupt to the write sequence.
The shift register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see Figure 44).
VDD
VOUT
GND
RESISTOR
NETWORK
REF (+)
REF (–)
OUTPUT
AMPLIFIER
DAC REGISTER
06853-
038
R
TO OUTPUT
AMPLIFIER
06853-
039
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD5621AKS | 制造商:AD 制造商全称:Analog Devices 功能描述:2.7 V to 5.5 V, <100 UA, 8-/10-/12-Bit nanoDAC D/A, SPI Interface, SC70 Package |
| AD5621AKSZ | 制造商:Analog Devices 功能描述:DAC SGL RES-STRING 12-BIT 6PIN SC-70 - Bulk |
| AD5621AKSZ-500RL7 | 功能描述:IC DAC 12BIT V-OUT SC70-6 RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:nanoDAC™ 标准包装:1 系列:- 设置时间:4.5µs 位数:12 数据接口:串行，SPI? 转换器数目:1 电压电源:单电源 功率耗散（最大）:- 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOICN 包装:剪切带 (CT) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:* 其它名称:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD5621AKSZ-REEL7 | 功能描述:IC DAC 12BIT 5V MICROPWR SC70-6 RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:nanoDAC™ 产品培训模块:Data Converter Fundamentals DAC Architectures 标准包装:3,000 系列:nanoDAC™ 设置时间:80µs 位数:18 数据接口:DSP，MICROWIRE?，QSPI?，串行，SPI? 转换器数目:1 电压电源:单电源 功率耗散（最大）:- 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:SOT-23-8 供应商设备封装:SOT-23-8 包装:带卷 (TR) 输出数目和类型:1 电压，单极 采样率（每秒）:- 产品目录页面:784 (CN2011-ZH PDF) 配用:EVAL-AD5680EBZ-ND - BOARD EVAL FOR AD5680 其它名称:AD5680BRJZ-2REEL7TR |
| AD5621BKS | 制造商:AD 制造商全称:Analog Devices 功能描述:2.7 V to 5.5 V, <100 UA, 8-/10-/12-Bit nanoDAC D/A, SPI Interface, SC70 Package |
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