参数资料
| 型号： | AD5626BRMZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 17/20页 |
| 文件大小： | 0K |
| 描述： | IC DAC NANO 12BIT 8-MSOP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 1 |
| 系列： | nanoDAC™ |
| 设置时间： | 16µs |
| 位数： | 12 |
| 数据接口： | 串行 |
| 转换器数目： | 1 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 12.5mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 8-MSOP |
| 包装： | 标准包装 |
| 输出数目和类型： | 1 电压，单极；1 电压，双极 |
| 采样率（每秒）： | * |
| 其它名称： | AD5626BRMZ-REEL7DKR |
AD5626
Rev. A | Page 6 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
0
67
57
-0
03
VDD 1
CS 2
SCLK 3
SDIN 4
VOUT
8
GND
7
CLR
6
LDAC
5
AD5626
TOP VIEW
(Not to Scale)
0
67
57
-0
04
VDD 1
SCLK 3
SDIN 4
VOUT
8
GND
7
AD5626
TOP VIEW
(Not to Scale)
CS 2
CLR
6
LDAC
5
Figure 3. 8-Lead MSOP Pin Configuration
Figure 4. 8-Lead LFCSP Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VDD
Positive Supply. Nominal value 5 V ± 5%.
2
CS
Chip Select. Active low input.
3
SCLK
Clock Input. Clock input for the internal serial input shift register.
4
SDIN
Serial Data Input. Data on this pin is clocked into the internal serial register on positive clock edges of the
SCLK pin. The most significant bit (MSB) is loaded first.
5
LDAC
Serial Register Data Write to DAC Register. Active low input that writes the serial register data into the DAC
register. Asynchronous input.
6
CLR
Clear DAC Register. Active low digital input that clears the DAC register to zero, setting the DAC to minimum
scale. Asynchronous input.
7
GND
Ground. Analog ground for the DAC. This also serves as the digital logic ground reference voltage.
8
VOUT
Voltage Output from the DAC. Fixed output voltage range of 0 V to 4.095 V with 1 mV/LSB. An internal
temperature stabilized reference maintains a fixed full-scale voltage independent of time, temperature, and
power supply variations.
Table 5. Control Logic Truth Table1
CLR
Serial Shift Register Function
DAC Register Function
H
X
H
No effect
Latched
L
H
No effect
Latched
L
H
No effect
Latched
L
↑+
H
Shift-register-data advanced one bit
Latched
↑+
L
H
Shift-register-data advanced one bit
Latched
H
X
H
↓–
No effect
Updated with current shift register contents
H
X
H
L
No effect
Transparent
H
X
L
X
No effect
Loaded with all zeros
H
X
↑+
H
No effect
Latched all zeros
1
↑+ indicates a positive logic transition; ↓– indicates a negative logic transition; X = don’t care.
2 CS and CLK are interchangeable.
3 Returning CS high avoids an additional false clock of serial data input.
4 Do not clock in serial data while LD is low.
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