参数资料
| 型号： | AD5626BRMZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/20页 |
| 文件大小： | 0K |
| 描述： | IC DAC NANO 12BIT 8-MSOP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 1 |
| 系列： | nanoDAC™ |
| 设置时间： | 16µs |
| 位数： | 12 |
| 数据接口： | 串行 |
| 转换器数目： | 1 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 12.5mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 8-MSOP |
| 包装： | 标准包装 |
| 输出数目和类型： | 1 电压，单极；1 电压，双极 |
| 采样率（每秒）： | * |
| 其它名称： | AD5626BRMZ-REEL7DKR |
AD5626
Rev. A | Page 13 of 20
OPERATING THE AD5626 ON 12 V OR 15 V
SUPPLIES ONLY
Although the AD5626 has been specified to operate on a single,
5 V supply, a single 5 V supply may not be available in many
applications. Because the AD5626 consumes no more than 2.5 mA
maximum, an integrated voltage reference, such as the ADR02,
can be used as the 5 V supply for the AD5626. See Figure 28 for
the circuit configuration. Notice that the output voltage of the
reference requires no trimming because of the excellent load
regulation and tight initial output voltage tolerance of the ADR02.
Although the maximum supply current of the AD5626 is 2.5 mA,
local bypassing of the ADR02 output with at least 0.1 μF at the
DAC voltage supply pin is recommended to prevent the internal
digital circuits of the DAC from affecting the internal voltage
reference of the DAC.
0
675
7-
0
28
CS
CLR
SCLK
LDAC
SDIN
2
8
6
5
3
4
1
7
VDD
GND
AD5626
0.1F
VOUT
12V OR 15V
1F
ADR02
2
4
6
Figure 28. Operating the AD5626 on 12 V or 15 V Supplies Using an
ADR02 Voltage Reference
MEASURING OFFSET ERROR
One of the most commonly specified endpoint errors associated
with real world nonideal DACs is offset error. In most DAC
testing, the offset error is measured by applying the zero-scale
code and measuring the output deviation from 0 V.
There are some DACs where offset errors are present but not
observable at the zero scale because of other circuit limitations
(for example, zero coinciding with single-supply ground). In
these DACs, nonzero output at zero code cannot be read as the
offset error. In the AD5626, for example, the zero-scale error is
specified to be ±3 LSBs. Because zero scale coincides with zero
volt, it is not possible to measure negative offset error.
0
67
57
-02
9
CS
CLR
SCLK
V–
LDAC
SDIN
2
8
6
5
3
4
VOUT
1
7
VDD
GND
AD5626
0.1F
5V
200A, MAX
R
VOUT
SET CODE = 0x000 AND MEASURE VOUT
Figure 29. Measuring Zero-Scale or Offset Error
By adding a pull-down resistor from the output of the AD5626
to a negative supply as shown in Figure 29, offset errors can be
read at zero code. This configuration forces the output P-channel
MOSFET to source current to the negative supply thereby allowing
the designer to determine in which direction the offset error
appears. The value of the resistor should be such that, at zero
code, current through the resistor is 200 μA, maximum.
BIPOLAR OUTPUT OPERATION
Although the AD5626 has been designed for single-supply
operation, bipolar operation is achievable using the circuit
illustrated in Figure 30. The circuit uses a single-supply, rail-
to-rail OP295 op amp and the REF03 to generate the 2.5 V
reference required to level shift the DAC output voltage.
Note that the 2.5 V reference is generated without the use of
precision resistors. The circuit configuration provides an output
voltage in the range of 5 V ≤ VOUT ≤ +5 V and is coded in comple-
mentary offset binary. Although each DAC LSB corresponds to
1 mV, each output LSB has been scaled to 2.44 mV. Table 7 lists
the relationship between the digital codes and output voltage.
The transfer function of the circuit is given by
R2
R4
R1
R4
Code
Digital
V
O
×
+
×
=
5
.
2
mV
1
and, for the circuit values shown, becomes
VO = 2.44 mV × Digital Code + 5 V
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