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| 型号： | AD5678BRUZ-1REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 16/28页 |
| 文件大小： | 0K |
| 描述： | IC DAC 12/16BIT SPI/SRL 14TSSOP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 1,000 |
| 设置时间： | 6µs |
| 位数： | 12，16 |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 8 |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 14-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 14-TSSOP |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 8 电压，单极 |
| 采样率（每秒）： | 95k |
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AD5678
Rev. C | Page 23 of 28
INTERNAL REFERENCE REGISTER
The on-board reference is off at power-up by default. This
allows the use of an external reference if the application requires
it. The on-board reference can be turned on/off by a user-
programmable internal REF register by setting Bit DB0 high or
low (see Table 9). Command 1000 is reserved for this internal
the bits in the input shift register corresponds to the mode of
operation of the device.
POWER-ON RESET
The AD5678 contains a power-on reset circuit that controls the
output voltage during power-up. The AD5678 output powers up
to 0 V, and the output remains powered up at this level until a
valid write sequence is made to the DAC. This is useful in
applications where it is important to know the state of the
output of the DAC while it is in the process of powering up.
There is also a software executable reset function that resets the
DAC to the power-on reset code. Command 0111 is reserved
for this reset function—see Table 7. Any events on LDAC or
CLR during power-on reset are ignored.
POWER-DOWN MODES
The AD5678 contains four separate modes of operation.
Command 0100 is reserved for the power-down function. See
Table 7. These modes are software-programmable by setting
two bits, Bit DB9 and Bit DB8, in the control register.
Table 11 shows how the state of the bits corresponds to the
mode of operation of the device. Any or all DACs (DAC H to
DAC A) can be powered down to the selected mode by setting
the corresponding eight bits (DB7 to DB0) to 1. See Table 12 for
the contents of the input shift register during power-down/power-
up operation. When using the internal reference, only all channel
power-down to the selected modes is supported.
When both bits are set to 0, the part works normally with its
normal power consumption of 1.3 mA at 5 V. However, for the
three power-down modes, the supply current falls to 400 nA at
5 V (200 nA at 3 V). Not only does the supply current fall, but
the output stage is also internally switched from the output of
the amplifier to a resistor network of known values. This has the
advantage that the output impedance of the part is known while
the part is in power-down mode. There are three different
options. The output is connected internally to GND through
either a 1 kΩ or a 100 kΩ resistor, or it is left open-circuited
(three-state). The output stage is illustrated in Figure 50.
The bias generator of the selected DAC(s), output amplifier,
resistor string, and other associated linear circuitry are shut
down when the power-down mode is activated. However, the
contents of the DAC register are unaffected when in power-
down. The time to exit power-down is typically 5 μs for
Any combination of DACs can be powered up by setting PD1
and PD0 to 0 (normal operation). The output powers up to the
value in the input register (LDAC low) or to the value in the
DAC register before powering down (LDAC high).
CLEAR CODE REGISTER
The AD5678 has a hardware CLR pin that is an asynchronous
clear input. The CLR input is falling edge sensitive . Bringing
the CLR line low clears the contents of the input register and the
DAC registers to the data contained in the user-configurable
CLR register and sets the analog outputs accordingly. This
function can be used in system calibration to load zero scale,
midscale, or full scale to all channels together. These clear code
values are user-programmable by setting two bits, Bit DB1 and Bit
DB0, in the CLR control register. See
. The default
setting clears the outputs to 0 V. Command 0101 is reserved for
loading the clear code register, see
.
The part exits clear code mode on the 32nd falling edge of the
next write to the part. If CLR is activated during a write
sequence, the write is aborted.
The CLR pulse activation time—the falling edge of CLR to when
the output starts to change—is typically 280 ns. However, if the
value is outside the linear region, it typically takes 520 ns after
executing CLR for the output to start changing. See
See Table 14 for contents of the input shift register during the
loading clear code register operation.
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