参数资料
| 型号： | AD5722AREZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/32页 |
| 文件大小： | 0K |
| 描述： | IC DAC DUAL 12BIT 1LSB 24TSSOP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 设计资源： | Software Configurable 12-Bit Dual-Channel Unipolar/Bipolar Voltage Output Using AD5722 (CN0094) |
| 标准包装： | 62 |
| 设置时间： | 10µs |
| 位数： | 12 |
| 数据接口： | 串行 |
| 转换器数目： | 2 |
| 电压电源： | 模拟和数字，双 ± |
| 功率耗散（最大）： | 190mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 供应商设备封装： | 24-TSSOP 裸露焊盘 |
| 包装： | 管件 |
| 输出数目和类型： | 2 电压，单极；2 电压，双极 |
| 采样率（每秒）： | * |
| 产品目录页面： | 784 (CN2011-ZH PDF) |
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AD5722/AD5732/AD5752
Rev. D | Page 19 of 32
Standalone Operation
The serial interface works with both a continuous and noncon-
tinuous serial clock. A continuous SCLK source can be used
only if SYNC is held low for the correct number of clock cycles.
In gated clock mode, a burst clock containing the exact number
of clock cycles must be used, and SYNC must be taken high
after the final clock to latch the data. The first falling edge of
SYNC starts the write cycle. Exactly 24 falling clock edges must
be applied to SCLK before SYNC is brought high again. If
SYNC is brought high before the 24th falling SCLK edge, the
data written is invalid. If more than 24 falling SCLK edges are
applied before SYNC is brought high, the input data is also
invalid. The input register addressed is updated on the rising
edge of SYNC. For another serial transfer to take place, SYNC
must be brought low again. After the end of the serial data
transfer, data is automatically transferred from the input shift
register to the addressed register.
When the data has been transferred into the chosen register of
the addressed DAC, all DAC registers and outputs can be
updated by taking LDAC low while SYNC is high.
*ADDITIONAL PINS OMITTED FOR CLARITY.
68HC11*
MISO
SDIN
SCLK
MOSI
SCK
PC7
PC6
SDO
SCLK
SDO
SCLK
SDO
SDIN
SYNC
LDAC
AD5722/
AD5732/
AD5752*
AD5722/
AD5732/
AD5752*
AD5722/
AD5732/
AD5752*
06
46
7-
0
08
Figure 40. Daisy Chaining the AD5722/AD5732/AD5752
Daisy-Chain Operation
For systems that contain several devices, the SDO pin can be
used to daisy-chain several devices together. Daisy-chain mode
can be useful in system diagnostics and in reducing the number
of serial interface lines. The first falling edge of SYNC starts the
write cycle. SCLK is continuously applied to the input shift
register when SYNC is low. If more than 24 clock pulses are
applied, the data ripples out of the shift register and appears on
the SDO line. This data is clocked out on the rising edge of
SCLK and is valid on the falling edge. By connecting the SDO
of the first device to the SDIN input of the next device in the
chain, a multidevice interface is constructed. Each device in the
system requires 24 clock pulses. Therefore, the total number of
clock cycles must equal 24 × N, where N is the total number of
AD5722/AD5732/AD5752 devices in the chain. When the serial
transfer to all devices is complete, SYNC is taken high. This
latches the input data in each device in the daisy chain and
prevents any further data from being clocked into the input shift
register. The serial clock can be a continuous or a gated clock.
A continuous SCLK source can only be used if SYNC is held
low for the correct number of clock cycles. In gated clock mode,
a burst clock containing the exact number of clock cycles must
be used, and SYNC must be taken high after the final clock to
latch the data.
Readback Operation
Readback mode is invoked by setting the R/W bit = 1 in the
write operation to the serial input shift register. (If the SDO
output is disabled via the SDO disable bit in the control register,
it is automatically enabled for the duration of the read operation,
after which it is disabled again.) With R/W = 1, Bit A2 to Bit A0,
in association with Bit REG2 to Bit REG0, select the register to
be read. The remaining data bits in the write sequence are don’t
care bits. During the next SPI write, the data appearing on the SDO
output contains the data from the previously addressed register.
For a read of a single register, the NOP command can be used in
clocking out the data from the selected register on SDO. The
readback diagram in
shows the readback sequence.
For example, to read back the DAC register of Channel A, the
following sequence should be implemented:
1.
Write 0x800000 to the AD5722/AD5732/AD5752 input
register. This configures the part for read mode with the
DAC register of Channel A selected. Note that all the data
bits, DB15 to DB0, are don’t care bits.
2.
Follow this with a second write, a NOP condition, 0x180000.
During this write, the data from the register is clocked out
on the SDO line.
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相关代理商/技术参数 |
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| AD5722AREZ-REEL7 | 功能描述:IC DAC DUAL 12BIT 1LSB 24TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:LTC263x 12-, 10-, and 8-Bit VOUT DAC Family 特色产品:LTC2636 - Octal 12-/10-/8-Bit SPI VOUT DACs with 10ppm/°C Reference 标准包装:91 系列:- 设置时间:4µs 位数:10 数据接口:MICROWIRE?，串行，SPI? 转换器数目:8 电压电源:单电源 功率耗散（最大）:2.7mW 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:14-WFDFN 裸露焊盘 供应商设备封装:14-DFN-EP（4x3） 包装:管件 输出数目和类型:8 电压，单极 采样率（每秒）:* |
| AD5722R | 制造商:AD 制造商全称:Analog Devices 功能描述:Complete, Dual, 12-/14-/16-Bit, Serial Input, Unipolar/Bipolar, Voltage Output DACs |
| AD5722RBREZ | 功能描述:IC DAC DUAL 12BIT 1LSB 24TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:50 系列:- 设置时间:4µs 位数:12 数据接口:串行 转换器数目:2 电压电源:单电源 功率耗散（最大）:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-TSSOP，8-MSOP（0.118"，3.00mm 宽） 供应商设备封装:8-uMAX 包装:管件 输出数目和类型:2 电压，单极 采样率（每秒）:* 产品目录页面:1398 (CN2011-ZH PDF) |
| AD5722RBREZ-REEL7 | 功能描述:IC DAC DUAL 12BIT 1LSB 24TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 标准包装:47 系列:- 设置时间:2µs 位数:14 数据接口:并联 转换器数目:1 电压电源:单电源 功率耗散（最大）:55µW 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:管件 输出数目和类型:1 电流，单极；1 电流，双极 采样率（每秒）:* |
| AD5724 | 制造商:AD 制造商全称:Analog Devices 功能描述:Complete, Quad, 12-/14-/16-Bit, Serial Input, Unipolar/Bipolar Voltage Output DACs |
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