参数资料
型号: AD5752AREZ
厂商: Analog Devices Inc
文件页数: 16/32页
文件大小: 0K
描述: IC DAC DUAL 16BIT SERIAL 24TSSOP
产品培训模块: Data Converter Fundamentals
DAC Architectures
设计资源: Software Configurable 16-Bit Dual-Channel Unipolar/Bipolar Voltage Output Using AD5752 (CN0092)
标准包装: 62
设置时间: 10µs
位数: 16
数据接口: 串行
转换器数目: 2
电压电源: 模拟和数字,双 ±
功率耗散(最大): 190mW
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-TSSOP(0.173",4.40mm)裸露焊盘
供应商设备封装: 24-TSSOP 裸露焊盘
包装: 管件
输出数目和类型: 2 电压,单极;2 电压,双极
采样率(每秒): *
产品目录页面: 784 (CN2011-ZH PDF)
AD5722/AD5732/AD5752
Rev. D | Page 23 of 32
Ideal Output Voltage to Input Code Relationship—AD5722
Table 13. Bipolar Output, Offset Binary Coding
Digital Input
Analog Output
MSB
LSB
±5 V Output Range
±10 V Output Range
±10.8 V Output Range
1111
+2 × REFIN × (2047/2048)
+4 × REFIN × (2047/2048)
+4.32 × REFIN × (2047/2048)
1111
1110
+2 × REFIN × (2046/2048)
+4 × REFIN × (2046/2048)
+4.32 × REFIN × (2046/2048)
1000
0000
0001
+2 × REFIN × (1/2048)
+4 × REFIN × (1/2048)
+4.32 × REFIN × (1/2048)
1000
0000
0 V
0111
1111
2 × REFIN × (1/2048)
4 × REFIN × (1/2048)
4.32 × REFIN × (1/2048)
0000
0001
2 × REFIN × (2046/2048)
4 × REFIN × (2046/2048)
4.32 × REFIN × (2046/2048)
0000
2 × REFIN × (2047/2047)
4 × REFIN × (2047/2048)
4.32 × REFIN × (2047/2048)
Table 14. Bipolar Output, Twos Complement Coding
Digital Input
Analog Output
MSB
LSB
±5 V Output Range
±10 V Output Range
±10.8 V Output Range
0111
1111
+2 × REFIN × (2047/2048)
+4 × REFIN × (2047/2048)
+4.32 × REFIN × (2047/2048)
0111
1111
1110
+2 × REFIN × (2046/2048)
+4 × REFIN × (2046/2048)
+4.32 × REFIN × (2046/2048)
0000
0001
+2 × REFIN × (1/2048)
+4 × REFIN × (1/2048)
+4.32 × REFIN × (1/2048)
0000
0 V
1111
2 × REFIN × (1/2048)
4 × REFIN × (1/2048)
4.32 × REFIN × (1/2048)
1000
0000
0001
2 × REFIN × (2046/2048)
4 × REFIN × (2046/2048)
4.32 × REFIN × (2046/2048)
1000
0000
2 × REFIN × (2047/2048)
4 × REFIN × (2047/2048)
4.32 × REFIN × (2047/2048)
Table 15. Unipolar Output, Straight Binary Coding
Digital Input
Analog Output
MSB
LSB
+5 V Output Range
+10 V Output Range
+10.8 V Output Range
1111
+2 × REFIN × (4095/4096)
+4 × REFIN × (4095/4096)
+4.32 × REFIN × (4095/4096)
1111
1110
+2 × REFIN × (4094/4096)
+4 × REFIN × (4094/4096)
+4.32 × REFIN × (4094/4096)
1000
0000
0001
+2 × REFIN × (2049/4096)
+4 × REFIN × (2049/4096)
+4.32 × REFIN × (2049/4096)
1000
0000
+2 × REFIN × (2048/4096)
+4 × REFIN × (2048/4096)
+4.32 × REFIN × (2048/4096)
0111
1111
+2 × REFIN × (2047/4096)
+4 × REFIN × (2047/4096)
+4.32 × REFIN × (2047/4096)
0000
0001
+2 × REFIN × (1/4096)
+4 × REFIN × (1/4096)
+4.32 × REFIN × (1/4096)
0000
0 V
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