参数资料
| 型号： | AD641AP-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/16页 |
| 文件大小： | 0K |
| 描述： | IC AMP LOG LP 2.3MA 20PLCC |
| 标准包装： | 250 |
| 放大器类型： | 对数 |
| 电路数： | 1 |
| -3db带宽： | 250MHz |
| 电流 - 输入偏压： | 7µA |
| 电压 - 输入偏移： | 50µV |
| 电流 - 电源： | 35mA |
| 电流 - 输出 / 通道： | 2.3mA |
| 电压 - 电源，单路/双路(±)： | ±4.5 V ~ 7.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-LCC（J 形引线） |
| 供应商设备封装： | 20-PLCC（9x9） |
| 包装： | 带卷 (TR) |
REV. C
AD641
–6–
ATN LO
ATN COM
SIG +IN
SIG –IN
ATN COM
COM
27
30
270
ATN IN
1k
RG1
RG0
RG2
–VS
BL1
+VS
LOG OUT
LOG COM
SIG +OUT
SIG –OUT
BL2
ITC
20
GAIN BIAS REGULATOR
AMPLIFIER/LIMITER
FULL-WAVE
DETECTOR
10dB
AMPLIFIER/LIMITER
FULL-WAVE
DETECTOR
10dB
AMPLIFIER/LIMITER
FULL-WAVE
DETECTOR
10dB
AMPLIFIER/LIMITER
FULL-WAVE
DETECTOR
10dB
AMPLIFIER/LIMITER
FULL-WAVE
DETECTOR
10dB
ATN OUT
1
2
3
6
4
5
19
18
7
13
9
8
11
10
12
SLOPE BIAS REGULATOR
INTERCEPT POSITIONING BIAS
14
15
16
17
Figure 17. Block Diagram of the Complete AD641
CIRCUIT DESCRIPTION
The AD641 uses five cascaded limiting amplifiers to approxi-
mate a logarithmic response to an input signal of wide dynamic
range and wide bandwidth. This type of logarithmic amplifier
has traditionally been assembled from several small scale ICs
and numerous external components. The performance of these
semidiscrete circuits is often unsatisfactory. In particular, the
logarithmic slope and intercept (see FUNDAMENTALS OF
LOGARITHMIC CONVERSION) are usually not very stable
in the presence of supply and temperature variations even after
laborious and expensive individual calibration. The AD641 em-
ploys high precision analog circuit techniques to ensure stability
of scaling over wide variations in supply voltage and tempera-
ture. Laser trimming, using ac stimuli and operating conditions
similar to those encountered in practice, provides fully cali-
brated logarithmic conversion.
Each of the amplifier/limiter stages in the AD641 has a small
signal voltage gain of 10 dB (
×3.162) and a –3 dB bandwidth of
350 MHz. Fully differential direct coupling is used throughout.
This eliminates the many interstage coupling capacitors usually
required in ac applications, and simplifies low frequency signal
processing, for example, in audio and sonar systems. The AD641
is intended for use in demodulating applications. Each stage
incorporates a detector (a full-wave transconductance rectifier)
whose output current depends on the absolute value of its input
voltage.
Figure 16 is a simplified schematic of one stage of the AD641.
All transistors in the basic cell operate at near zero collector to
base voltage and low bias currents, resulting in low levels of
thermally induced distortion. These arise when power shifts
from one set of transistors to another during large input signals.
Rapid recovery is essential when a small signal immediately
follows a large one. This low power operation also contributes
significantly to the excellent long term calibration stability of the
AD641.
The complete AD641, shown in Figure 17, includes two bias
regulators. One determines the small signal gain of the ampli-
fier stages; the other determines the logarithmic slope. These
bias regulators maintain a high degree of stability in the re-
sulting function by compensating for potentially large uncer-
tainties in transistor parameters, temperature and supply
voltages. A third biasing block is used to accurately control
the logarithmic intercept.
COMMON
SIG
IN
R1
85
R2
85
R3
75
R4
75
SIG
OUT
LOG OUT
LOG COM
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q10
Q9
–VS
1.09mA
PTAT
1.09mA
PTAT
565 A
2.18mA
PTAT
Figure 16. Simplified Schematic of a Single AD641 Stage
By summing the signals at the output of the detectors, a good
approximation to a logarithmic transfer function can be achieved.
The lower the stage gain, the more accurate the approximation,
but more stages are then needed to cover a given dynamic range.
The choice of 10 dB results in a theoretical periodic deviation or
ripple in the transfer function of
±0.15 dB from the ideal re-
sponse when the input is either a dc voltage or a square wave.
The slope of the transfer function is unaffected by the input
waveform; however, the intercept and ripple are waveform de-
pendent (see EFFECT OF WAVEFORM ON INTERCEPT).
The input will usually be an amplitude modulated sinusoidal
carrier. In these circumstances the output is a fluctuating cur-
rent at twice the carrier frequency (because of the full wave
detection) whose average value is extracted by an external low
pass filter, which recovers a logarithmic measure of the base-
band signal.
Circuit Operation
With reference to Figure 16, the transconductance pair Q7, Q8
and load resistors R3 and R4 form a limiting amplifier having a
small signal gain of 10 dB, set by the tail current of nominally
2.18 mA at 27
°C. This current is basically proportional to abso-
lute temperature (PTAT) but includes additional current to
compensate for finite beta and junction resistance. The limiting
output voltage is
±180 mV at +27°C and is PTAT. Emitter
followers Q1 and Q2 raise the input resistance of the stage,
provide level shifting to introduce collector bias for the gain
stage and detectors, reduce offset drift by forming a thermally
balanced quad with Q7 and Q8 and generate the detector bias-
ing across resistors R1 and R2.
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相关代理商/技术参数 |
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| AD641APZ | 功能描述:IC AMP LOG LP 2.3MA 20PLCC RoHS:是 类别:集成电路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 标准包装:50 系列:- 放大器类型:J-FET 电路数:2 输出类型:- 转换速率:3.5 V/µs 增益带宽积:1MHz -3db带宽:- 电流 - 输入偏压:30pA 电压 - 输入偏移:2000µV 电流 - 电源:200µA 电流 - 输出 / 通道:- 电压 - 电源，单路/双路(±):7 V ~ 36 V，±3.5 V ~ 18 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:8-DIP（0.300"，7.62mm） 供应商设备封装:8-PDIP 包装:管件 |
| AD641-EB | 制造商:Analog Devices 功能描述:AD641 EVALUATION BOARD - Bulk |
| AD641N | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Amplifier. Other |
| AD641P | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Amplifier. Other |
| AD641Q | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Amplifier. Other |
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