参数资料
型号: AD654
厂商: Analog Devices, Inc.
英文描述: Low Cost Monolithic Voltage-to-Frequency Converter(低成本单片电压-频率转换器)
中文描述: 低成本单片电压频率转换器(低成本单片电压-频率转换器)
文件页数: 4/8页
文件大小: 307K
代理商: AD654
AD654
REV. A
–4–
Figure 4. Current Source FS Trim
resistor R1, and flowing into Pin 3; it constitutes the signal
current I
T
to be converted. The second path, through another
100
resistor R2, carries the same nominal current. Two equal
valued resistors offer the best overall stability, and should be
either 1% discrete film units, or a pair from a common array.
Since the 1 mA FS input current is divided into two 500
μ
A legs
(one to ground and one to Pin 3), the total input signal current
(I
S
) is divided by a factor of two in this network. To achieve the
same conversion scale factor, C
T
must be reduced by a factor of
two. This results in a transfer unique to this hookup:
f
=
I
S
(20
V
)
C
T
For calibration purposes, resistors R3 and R4 are added to the
network, allowing a
±
15% trim of scale factor with the values
shown. By varying R4’s value the trim range can be modified to
accommodate wider tolerance components or perhaps the cali-
bration tolerance on a current output transducer such as the
AD592 temperature sensor. Although the values of R1–R4
shown are valid for 1 mA FS signals only, they can be scaled
upward proportionately for lower FS currents. For instance, they
should be increased by a factor of ten for a FS current of 100
μ
A.
In addition to the offsets generated by the input amplifier’s bias
and offset currents, an offset voltage induced parasitic current
arises from the current fork input network. These effects are
minimized by using the bias current compensation resistor R
OFF
and offset trim scheme shown in Figure 3e.
Although device warm-up drifts are small, it is good practice to
allow the devices operating environment to stabilize before trim,
and insure the supply, source and load are appropriate. If provision
is made to trim offset, begin by setting the input to 1/10,000 of
full scale. Adjust the offset pot until the output is 1/10,000 of
full scale (for example, 25 Hz for a FS of 250 kHz). This is most
easily accomplished using a frequency meter connected to the
output. The FS input should then be applied and the gain pot
should be adjusted until the desired FS frequency is indicated.
INPUT PROTECTION
The AD654 was designed to be used with a minimum of addi-
tional hardware. However, the successful application of a preci-
sion IC involves a good understanding of possible pitfalls and
the use of suitable precautions. Thus +V
IN
and R
T
pins should
not be driven more than 300 mV below –V
S
. Likewise, Logic
Common should not drop more than 500 mV below –V
S
. This
would cause internal junctions to conduct, possibly damaging
the IC. In addition to the diode shown in Figures 1 and 2 pro-
tecting Logic Common, a second Schottky diode (MBD101)
can protect the AD654’s inputs from “below –V
S
’’ inputs as
Figure 3c. Offset Trim Positive Input (10 V FS)
Figure 3d. Offset Trim Negative Input (–10 V FS)
Figure 3e. Offset Trim Bias Network
FULL-SCALE CALIBRATION
Full-scale trim is the calibration of the circuit to produce the
desired output frequency with a full-scale input applied. In most
cases this is accomplished by adjusting the scaling resistor R
T
.
Precise calibration of the AD654 requires the use of an accurate
voltage standard set to the desired FS value and an accurate fre-
quency meter. A scope is handy for monitoring output wave-
shape. Verification of converter linearity requires the use of a
switchable voltage source or DAC having a linearity error below
±
0.005%, and the use of long measurement intervals to mini-
mize count uncertainties. Since each AD654 is factory tested for
linearity, it is unnecessary for the end-user to perform this tedious
and time consuming test on a routine basis.
Sufficient FS calibration trim range must be provided to accom-
modate the worst-case sum of all major scaling errors. This in-
cludes the AD654’s 10% full-scale error, the tolerance of the
fixed scaling resistor, and the tolerance of the timing capacitor.
Therefore, with a resistor tolerance of 1% and a capacitor toler-
ance of 5%, the fixed part of the scaling resistor should be a
maximum of 84% of nominal, with the variable portion selected
to allow 116% of the nominal.
If the input is in the form of a negative current source, the scal-
ing resistor is no longer required, eliminating the capability of
trimming FS frequency in this fashion. Since it is usually not
practical to smoothly vary the capacitance for trimming pur-
poses, an alternative scheme such as the one shown in Figure 4
is needed. Designed for a FS of 1 mA, this circuit divides the
input into two current paths. One path is through the 100
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