参数资料
型号: AD6600AST
厂商: ANALOG DEVICES INC
元件分类: ADC
英文描述: Dual Channel, Gain-Ranging ADC with RSSI
中文描述: 2-CH 11-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP44
封装: PLASTIC, LQFP-44
文件页数: 2/24页
文件大小: 303K
代理商: AD6600AST
REV. 0
–2–
AD6600–SPECIFICATIONS
DC SPECIFICATIONS
Test
Level
AD6600AST
Typ
Parameter
ANALOG INPUTS (AIN,
AIN
/BIN,
BIN
)
Differential Analog Input Voltage Range
1
Differential Analog Input Resistance
2
Differential Analog Input Capacitance
PEAK DETECTOR (Internal), RSSI
Resolution
RSSI Gain Step
RSSI Hysteresis
3
RESONANT PORT (FLT,
FLT
)
Differential Port Resistance
Differential Port Capacitance
A/D CONVERTER
Resolution
ENCODE INPUTS (ENC,
ENC
)
Differential Input Voltage (AC-Coupled)
4
Differential Input Resistance
Differential Input Capacitance
A/B MODE INPUTS (A_SEL, B_SEL)
5
Input High Voltage Range
Input Low Voltage Range
POWER SUPPLY
Supply Voltages
AVCC
DVCC
Supply Current
I
AVCC
(AVCC = 5.0 V)
I
DVCC
(DVCC = 3.3 V)
POWER CONSUMPTION
6
Temp
Min
Max
Unit
Full
Full
25
°
C
V
IV
V
2.0
200
1.5
V p-p
pF
160
240
3
6
6
Bits
dB
dB
Full
Full
V
V
Full
Full
V
V
630
1.75
pF
Full
IV
11
Bits
Full
25
°
C
25
°
C
IV
V
V
0.4
V p-p
k
pF
11
2.5
Full
Full
IV
IV
4.75
0.0
5.25
0.5
V
V
Full
Full
II
IV
4.75
3.0
5.0
3.3
5.25
5.25
V
V
Full
Full
Full
II
II
II
145
15
775
182
20
976
mA
mA
mW
NOTES
1
Analog Input Range is a function of input frequency. See ac specifications for 70 MHz–250 MHz inputs.
2
Analog Input Impedance is a function of input frequency. See ac specifications for 70 MHz–450 MHz inputs.
3
Six dB of digital hysteresis is used to eliminate level uncertainty at the RSSI threshold points due to noise and amplitude variations.
4
Encode inputs should be ac-coupled and driven differentially. See Encoding the AD6600 for details.
5
A_SEL and B_SEL should be tied directly to ground or AVCC.
6
Maximum power consumption is computed as maximum current at nominal supplies.
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
(AVCC = 5 V, DVCC = 3.3 V; T
MIN
= –40 C, T
MAX
= +85 C unless otherwise noted.)
Test
Level
AD6600AST
Typ
Parameter
LOGIC OUTPUTS (D10–D0, AB_OUT, RSSI2–0)
1
Logic Compatibility
Logic “1” Voltage (DVCC = 3.3 V)
Logic “0” Voltage (DVCC = 3.3 V)
Logic “1” Voltage (DVCC = 5.0 V)
Logic “0” Voltage (DVCC = 5.0 V)
Output Coding (D10–D0)
CLK2
×
OUTPUT
1, 2
Logic “1” Voltage (DVCC = 3.3 V)
Logic “0” Voltage (DVCC = 3.3 V)
Logic “1” Voltage (DVCC = 5.0 V)
Logic “0” Voltage (DVCC = 5.0 V)
Temp
Min
Max
Unit
CMOS
DVCC – 0.2
0.2
DVCC – 0.35
0.35
Two’s Complement
Full
Full
Full
Full
II
II
IV
IV
2.8
V
V
V
V
0.5
4.0
0.5
Full
Full
Full
Full
II
II
IV
IV
2.8
DVCC – 0.2
0.2
DVCC – 0.3
0.35
V
V
V
V
0.5
4.0
0.5
NOTES
1
Digital output load is one LCX gate.
2
CLK2
×
output voltage levels, high and low, tested at switching rate of 10 MHz.
Specifications subject to change without notice.
(AVCC = 5 V, DVCC = 3.3 V; T
MIN
= –40 C, T
MAX
= +85 C unless otherwise noted.)
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