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参数资料
| 型号： | AD6600ASTZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 19/24页 |
| 文件大小： | 0K |
| 描述： | IC ADC DUAL W/RSSI 44-LQFP T/R |
| 标准包装： | 1,500 |
| 位数： | 11 |
| 采样率（每秒）： | 20M |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 976mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-LQFP |
| 供应商设备封装： | 44-LQFP（10x10） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 2 个差分，双极 |
REV. 0
–4–
AD6600–SPECIFICATIONS
TIMING REQUIREMENTS AND SWITCHING SPECIFICATIONS
1, 2
(AVCC = 5 V, DVCC = 3.3 V; ENC and
ENC = 20 MSPS, Duty Cycle = 50%; T
MIN = –40 C, TMAX = +85 C unless otherwise noted.)
Test
AD6600AST
Parameter
Name
Temp
Level
Min
Typ
Max
Unit
ENCODE/CLK2
×
Encode Rising to CLK2
× Falling3
tCF
Full
IV
6.5
8.0
9.5
ns
Encode Rising to CLK2
× Rising4
tCR
Full
IV
tCF + (tENCH)/2
ns
@ Encode = 13 MSPS, 50% Duty Cycle
Full
IV
25.7
27.2
28.7
ns
@ Encode = 20 MSPS, 50% Duty Cycle
Full
IV
19.0
20.5
22.0
ns
CLK2
×/DATA (D10:0, RSSI2:0)5
CLK2
× to DATA Rising Low Delay3
t2×_DRL
Full
IV
3.0
6.5
ns
CLK2
× to DATA Hold Time3
tH_D2×
Full
IV
3.0
6.5
ns
CLK2
× to DATA Falling Low3, 6
t2×_DFL
25
°C
IV
10.0
15.0
20.0
ns
Full
IV
11.0
15.5
22.0
ns
CLK2
× to DATA Setup Time4
tS_D2×
Full
IV
tENCH – t2×_DFL
ns
@ Encode = 13 MSPS, 50% Duty Cycle
Full
IV
16.5
23.0
ns
@ Encode = 20 MSPS, 50% Duty Cycle
6
25
°C
IV
5.0
10.0
ns
Full
IV
3.0
9.5
ns
CLK2
×/AB_OUT5
CLK2
× to AB_OUT Rising Low Delay3
t2×_ARL
Full
IV
7.0
11.0
ns
CLK2
× to AB_OUT Hold Time3
tH_A2×
Full
IV
7.0
11.0
ns
CLK2
× to AB_OUT Falling Low Delay3, 6
t2×_AFL
25
°C
IV
12.0
18.0
23.0
ns
Full
IV
10.7
19.0
26.0
ns
CLK2
× to AB_OUT Setup Time4
tS_A2×
Full
IV
tENCH – t2×_AFL
ns
@ Encode = 13 MSPS, 50% Duty Cycle
Full
IV
12.5
19.5
ns
@ Encode = 20 MSPS, 50% Duty Cycle6
25
°C
IV
2.0
7.0
ns
Full
IV
–1.0
6.0
ns
ENCODE/DATA (D10:0, RSSI2:0)
ENCODE to DATA Rising Low Delay
4
tEN_DRL
Full
IV
tCR + t2×_DRL
ns
ENCODE to DATA Hold Time
4
tH_DEN
Full
IV
tEN_DRL
ns
@ Encode = 13 MSPS, 50% Duty Cycle
Full
IV
28.7
33.7
ns
@ Encode = 20 MSPS, 50% Duty Cycle
Full
IV
22.0
27.0
ns
ENCODE to DATA Falling Low Delay
4
tEN_DFL
Full
IV
tCR + t2×_DFL
ns
ENCODE to DATA Delay (Setup)
4
tS_DEN
Full
IV
tENC – tEN_DFL
ns
@ Encode = 13 MSPS, 50% Duty Cycle
Full
IV
26.2
34.2
ns
@ Encode = 20 MSPS, 50% Duty Cycle
6
25
°C
IV
8.0
14.5
ns
Full
IV
6.0
14.0
ns
ENCODE/AB_OUT
ENCODE to AB_OUT Rising Low Delay
4
tEN_ARL
Full
IV
tCR + t2×_ARL
ns
ENCODE to AB_OUT Delay (Hold)
4
tH_AEN
Full
IV
tEN_ARL
ns
@ Encode = 13 MSPS, 50% Duty Cycle
Full
IV
32.7
38.2
ns
@ Encode = 20 MSPS, 50% Duty Cycle
Full
IV
26.0
31.5
ns
ENCODE to AB_OUT Falling Low Delay
4
tEN_AFL
Full
IV
tCR + t2×_AFL
ns
ENCODE to AB_OUT Delay (Setup)
4
tS_AEN
Full
IV
tENC – tEN_AFL
ns
@ Encode = 13 MSPS, 50% Duty Cycle
Full
IV
22.2
30.7
ns
@ Encode = 20 MSPS, 50% Duty Cycle
6
25
°C
IV
5.0
11.5
ns
Full
IV
2.0
10.5
ns
NOTES
1See AD6600 Timing Diagrams.
2All switching specifications tested by driving ENC and
ENC differentially.
3This specification IS NOT a function of Encode period and duty cycle.
4This specification IS a function of Encode period and duty cycle.
5CLK2
× referenced to 2.0 V crossing; digital output levels referenced to 0.8 V and 2.0 V crossings; all outputs with 10 pF load.
6For these particular specifications, the 25
°C specification is valid from 25°C to 85°C. The Full temperature specification includes cold temperature extreme and
covers the entire range, –40
°C to +85°C.
Specifications subject to change without notice.
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