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参数资料
| 型号： | AD660BR |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | DAC |
| 英文描述： | Monolithic 16-Bit Serial/Byte DACPORT |
| 中文描述： | SERIAL, PARALLEL, 8 BITS INPUT LOADING, 2.5 us SETTLING TIME, 16-BIT DAC, PDSO24 |
| 封装： | SOIC-24 |
| 文件页数： | 6/12页 |
| 文件大小： | 426K |
| 代理商： | AD660BR |
AD660
REV. A
–6–
SIGNAL-TO-NOISE RATIO: The signal-to-noise ratio is de-
fined as the ratio of the amplitude of the output when a full-
scale signal is present to the output with no signal present. This
is measured in dB.
DIGITAL-TO-ANALOG GLITCH IMPULSE: This is the
amount of charge injected from the digital inputs to the analog
output when the inputs change state. This is measured at half
scale when the DAC switches around the MSB and as many
as possible switches change state, i.e., from 011 . . . 111 to
100 . . . 000.
DIGITAL FEEDTHROUGH: When the DAC is not selected
(i.e.,
CS
is held high), high frequency logic activity on the digi-
tal inputs is capacitively coupled through the device to show up
as noise on the V
OUT
pin. This noise is digital feedthrough.
THEORY OF OPERATION
The AD660 uses an array of bipolar current sources with MOS
current steering switches to develop a current proportional to
the applied digital word, ranging from 0 to 2 mA. A segmented
architecture is used, where the most significant four data bits are
thermometer decoded to drive 15 equal current sources. The
lesser bits are scaled using a R-2R ladder, then applied together
with the segmented sources to the summing node of the output
amplifier. The internal span/bipolar offset resistor can be con-
nected to the DAC output to provide a 0 V to +10 V span, or it
can be connected to the reference input to provide a –10 V to
+10 V span.
16-BIT LATCH
16-BIT DAC
CONTROL
LOGIC
+10V REF
16-BIT LATCH
20
24
22
21
5
11
12
16
15
14
13
17
18
19
23
AD660
10k
10.05k
10k
SIN/
DB0
DB7
S
OUT
SPAN/
BIP
OFFSET
V
OUT
AGND
REF OUT
REF IN
LDAC
SER
DGND
–V
EE
+V
CC
+V
LL
1
2
3
4
LBE
CS
HBE
CLR
MSB/LSB/
DB1
UNI/BIP CLR/
Figure 2. AD660 Functional Block Diagram
ANALOG CIRCUIT CONNECTIONS
Internal scaling resistors provided in the AD660 may be con-
nected to produce a unipolar output range of 0 V to +10 V or a
bipolar output range of –10 V to +10 V. Gain and offset drift
are minimized in the AD660 because of the thermal tracking of
the scaling resistors with other device components.
UNIPOLAR CONFIGURATION
The configuration shown in Figure 3a will provide a unipolar
0 V to +10 V output range. In this mode, 50
resistors are tied
between the span/bipolar offset terminal (Pin 22) and V
OUT
(Pin 21), and between REF OUT (Pin 24) and REF IN (Pin
23). It is possible to use the AD660 without any external compo-
nents by tying Pin 24 directly to Pin 23 and Pin 22 directly to
Pin 21. Eliminating these resistors will increase the gain error by
0.25% of FSR.
16-BIT LATCH
16-BIT DAC
CONTROL
LOGIC
+10V REF
16-BIT LATCH
20
24
22
21
5
11
12
16
15
14
13
17
18
19
23
AD660
10k
10.05k
10k
HBE
LBE
CS
SIN/
DB0
MSB/LSB/
DB1
DB7
S
OUT
SPAN/
BIP OFF
V
OUT
AGND
REF OUT
REF IN
LDAC
CLR
SER
DGND
–V
EE
+V
CC
+V
LL
1
2
3
4
R1 50
OUTPUT
R2
50
UNI/BIP CLR/
Figure 3a. 0 V to +10 V Unipolar Voltage Output
If it is desired to adjust the gain and offset errors to zero, this can
be accomplished using the circuit shown in Figure 3b. The ad-
justment procedure is as follows:
STEP 1 . . . ZERO ADJUST
Turn all bits OFF and adjust zero trimmer, R4, until the output
reads 0.000000 volts (1 LSB = 153
μ
V).
STEP 2 . . . GAIN ADJUST
Turn all bits ON and adjust gain trimmer, R1, until the output is
9.999847 volts. (Full scale is adjusted to 1 LSB less than the
nominal full scale of 10.000000 volts).
16-BIT LATCH
16-BIT DAC
CONTROL
LOGIC
+10V REF
16-BIT LATCH
20
24
22
21
5
11
12
16
15
14
13
17
18
19
23
AD660
10k
10.05k
10k
HBE
LBE
CS
SIN/
DB0
MSB/LSB/
DB1
DB7
S
OUT
SPAN/
BIP OFF
REF OUT
REF IN
LDAC
CLR
SER
DGND
–V
EE
+V
CC
+V
LL
1
2
3
4
OUTPUT
R2
50
R4
10k
+V
CC
–V
EE
R1 100
AGND
UNI/BIP CLR/
Figure 3b. 0 V to +10 V Unipolar Voltage Output with Gain
and Offset Adjustment
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