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参数资料
| 型号： | AD677KRZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/16页 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT 100KSPS 28-SOIC |
| 标准包装： | 1,000 |
| 位数： | 16 |
| 采样率（每秒）： | 100k |
| 数据接口： | DSP，串行 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 480mW |
| 电压电源： | 模拟和数字，双 ± |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC W |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个单端，双极 |
| 配用： | AD677-EB-ND - BOARD EVAL SAMPLING ADC AD677 |
AD677
REV. A
–13–
The standard deviation of this distribution is approximately
0.5 LSBs. If less uncertainty is desired, averaging multiple con-
versions will narrow this distribution by the inverse of the square
root of the number of samples; i.e., the average of 4 conversions
would have a standard deviation of 0.25 LSBs.
DSP INTERFACE
Figure 10 illustrates the use of the Analog Devices ADSP-2101
digital signal processor with the AD677. The ADSP-2101 FO
(flag out) pin of Serial Port 1 (SPORT 1) is connected to the
SAMPLE line and is used to control acquisition of data. The
ADSP-2101 timer is used to provide precise timing of the FO
pin.
ADSP-2101
FO
AD677
SAMPLE
SERIAL
PORT 0
CLK
BUSY
SCLK0
DR0
RFS0
DT0
TFS0
SDATA
Figure 10. ADSP-2101 Interface
The SCLK pin of the ADSP-2101 SPORT0 provides the CLK
input for the AD677. The clock should be programmed to be
approximately 2 MHz to comply with AD677 specifications. To
minimize digital feedthrough, the clock should be disabled (by
setting Bit 14 in SPORT0 control register to 0) during data ac-
quisition. Since the clock floats when disabled, a pulldown resis-
tor of 12 k
–15 k should be connected to SCLK to ensure it
will be LOW at the falling edge of SAMPLE. To maximize the
conversion rate, the serial clock should be enabled immediately
after SAMPLE is brought LOW (hold mode).
The AD677 BUSY signal is connected to RF0 to notify
SPORT0 when a new data word is coming. SPORT0 should be
configured in normal, external, noninverting framing mode and
can be programmed to generate an interrupt after the last data
bit is received. To maximize the conversion rate, SAMPLE
should be brought HIGH immediately after the last data bit is
received.
102
9.5
86
82
2.5
90
94
98
8.5
4.5
3.5
V
REF – Volts
dB
106
5.5
6.5
7.5
THD
S/(N+D)
10.0
Figure 11. S/(N+D) and THD vs. VREF, fS = 100 kHz (Calibra-
tion is not guaranteed below +5 VREF)
INPUT LEVEL – dB
105
10
0
40
20
–70
30
–80
70
50
60
80
90
100
–10
–20
–30
–40
–50
–60
THD
S/(N+D)
dB
Figure 12. S/(N+D) and THD vs. Input Amplitude,
fS = 100 kHz
0
–20
–40
–60
–80
–100
–120
–140
0
51015
20
25
30
35
40
45
50
FREQUENCY – kHz
AMPLITUDE
–
dB
Figure 13. 4096 Point FFT at 100 kSPS, fIN = 1 kHz,
VREF = 5 V
0
–20
–40
–60
–80
–100
–120
–140
0
5
10
15
20
25
30
35
40
45
48
FREQUENCY – kHz
AMPLITUDE
–
dB
Figure 14. 4096 Point FFT at 100 kSPS, fIN = 1 kHz,
VREF = 10 V
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD677TD | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MICROCIRCUIT, DIGITAL-LINEAR, FAST, SERIAL, 16-BIT, A/D CONVERTER, MULTICHIP SILICON |
| AD677TD/883B | 功能描述:模数转换器 - ADC IC 16-BIT Serial 100 kSPS SAMPLING RoHS:否 制造商:Analog Devices 通道数量: 结构: 转换速率: 分辨率: 输入类型: 信噪比: 接口类型: 工作电源电压: 最大工作温度: 安装风格: 封装 / 箱体: |
| AD677TD883B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MICROCIRCUIT, DIGITAL-LINEAR, FAST, SERIAL, 16-BIT, A/D CONVERTER, MULTICHIP SILICON |
| AD678 | 制造商:AD 制造商全称:Analog Devices 功能描述:12-Bit 200 kSPS Complete Sampling ADC |
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