- 您现在的位置：买卖IC网 > PDF目录1891 > AD7142ACPZ-500RL7 (Analog Devices Inc)IC CAP-TO-DGTL CONV PROG 32LFCSP PDF资料下载
参数资料
| 型号： | AD7142ACPZ-500RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/73页 |
| 文件大小： | 0K |
| 描述： | IC CAP-TO-DGTL CONV PROG 32LFCSP |
| 标准包装： | 1 |
| 类型： | 电容数字转换器 |
| 分辨率（位）： | 16 b |
| 采样率（每秒）： | 250k |
| 数据接口： | 串行 |
| 电压电源： | 单电源 |
| 电源电压： | 2.6 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-VQ（5x5） |
| 包装： | 标准包装 |
| 其它名称： | AD7142ACPZ-500RL7DKR |
第1页第2页第3页第4页第5页第6页第7页当前第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页
AD7142
Rev. A | Page 15 of 72
CAPACITANCE-TO-DIGITAL CONVERTER
The capacitance-to-digital converter on the AD7142 has a Σ-Δ
architecture with 16-bit resolution. There are 14 possible inputs to
the CDC that are connected to the input of the converter through a
switch matrix. The sampling frequency of the CDC is 250 kHz.
OVERSAMPLING THE CDC OUTPUT
The decimation rate, or oversampling ratio, is determined by
Bits[9:8] of the control register, as listed in Table 9.
Table 9. CDC Decimation Rate
Decimation Bit Value
Decimation Rate
CDC Output Rate
Per Stage
00
256
3.072 ms
01
128
1.536 ms
–
–
1 Do not use this setting.
The decimation process on the AD7142 is an averaging process
where a number of samples are taken and the averaged result is
output. Due to the architecture of the digital filter employed, the
amount of samples taken (per stage) is equal to 3 times the
decimation rate. So 3 × 256 or 3 × 128 samples are averaged to
obtain each stage result.
The decimation process reduces the amount of noise present in
the final CDC result. However, the higher the decimation rate,
the lower the output rate per stage, thus, a trade-off is possible
between a noise-free signal and speed of sampling.
CAPACITANCE SENSOR OFFSET CONTROL
There are two programmable DACs on board the AD7142 to
null any capacitance sensor offsets. These offsets are associated
with printed circuit board capacitance or capacitance due to any
capacitance of the input sensors, and CBULK is the capacitance
between layers of the sensor PCB. CBULK can be offset using the
on-board DACs.
PLASTIC OVERLAY
SENSOR BOARD
CBULK
CIN
CAPACITIVE SENSOR
05
70
2-
05
4
Figure 22. Capacitances Around the Sensor PCB
A simplified block diagram in Figure 23 shows how to apply the
STAGE_OFFSET registers to null the offsets. The 7-bit
POS_AFE_OFFSET and NEG_AFE_OFFSET registers program
the offset DAC to provide 0.16 pF resolution offset adjustment
over a range of ±20 pF. Apply the positive and negative offsets
to either the positive or the negative CDC input using the
NEG_AFE_OFFSET register and POS_AFE_OFFSET register.
This process is only required once during the initial capacitance
sensor characterization.
05
70
2-
0
1
POS_AFE_OFFSET
16-BIT
CDC
NEG_AFE_OFFSET
+DAC
(20pF RANGE)
POS_AFE_OFFSET_SWAP BIT
NEG_AFE_OFFSET_SWAP BIT
7
16
CIN
SRC
CIN_CONNECTION_SETUP
REGISTER
SE
N
SO
R
–DAC
(20pF RANGE)
+
_
Figure 23. Analog Front-End Offset Control
CONVERSION SEQUENCER
The AD7142 has an on-chip sequencer to implement
conversion control for the input channels. Up to 12 conversion
stages can be performed in one sequence. Each of the 12
conversion stages can measure the input from a different sensor. By
using the Bank 2 registers, each stage can be uniquely configured to
support multiple capacitance sensor interface requirements. For
example, a slider sensor can be assigned to STAGE1 through
STAGE8, with a button sensor assigned to STAGE0.
The AD7142 on-chip sequence controller provides conversion
control beginning with STAGE0. Figure 24 shows a block diagram of
the CDC conversion stages and CIN inputs. A conversion sequence is
defined as a sequence of CDC conversions starting at STAGE0 and
ending at the stage determined by the value programmed in the
SEQUENCE_STAGE_NUM register. Depending on the number and
type of capacitance sensors that are used, not all conversion stages are
required. Use the SEQUENCE_STAGE_NUM register to set the
number of conversions in one sequence, depending on the sensor
interface requirements. For example, this register would be set to 5 if
the CIN inputs were mapped to only six stages. In addition, set the
STAGE_CAL_EN registers according to the number of stages that
are used.
相关PDF资料 |
PDF描述 |
|---|---|
| AD7143ACPZ-1REEL | IC CONV CAP-TO-DGTL PROG 16LFCSP |
| AD7147A-1ACBZ500R7 | IC CDC 13CH I2C W/RAM 25WLCSP |
| AD7147WPACPZ-1500R | IC CAP-TO-DGTL CONV PROG 24LFCSP |
| AD7150BRMZ-REEL | IC CAP CONV 2CH ULT LP 10MSOP |
| AD7151BRMZ-REEL | IC CAP CONV 1CH ULT LP 10MSOP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD7142ACPZ-500RL71 | 制造商:AD 制造商全称:Analog Devices 功能描述:Programmable Controller for Capacitance Touch Sensors |
| AD7142ACPZ-REEL | 功能描述:IC CAP-TO-DGTL CONV PROG 32LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - ADCs/DAC - 专用型 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:50 系列:- 类型:数据采集系统（DAS） 分辨率（位）:16 b 采样率（每秒）:21.94k 数据接口:MICROWIRE?，QSPI?，串行，SPI? 电压电源:模拟和数字 电源电压:1.8 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:40-WFQFN 裸露焊盘 供应商设备封装:40-TQFN-EP（6x6） 包装:托盘 |
| AD7142ACPZ-REEL1 | 制造商:AD 制造商全称:Analog Devices 功能描述:Programmable Controller for Capacitance Touch Sensors |
| AD7143 | 制造商:AD 制造商全称:Analog Devices 功能描述:Programmable Controller for Capacitance Touch Sensors |
| AD7143ACPZ | 制造商:Analog Devices 功能描述:IC CDC 16BIT SMD LFCSP-16 7143 制造商:Analog Devices 功能描述:IC, CDC, 16BIT, SMD, LFCSP-16, 7143 |
发布紧急采购，3分钟左右您将得到回复。