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| 型号： | AD7143ACPZ-1500RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 7/57页 |
| 文件大小： | 0K |
| 描述： | IC CTLR PROGRAMMABLE CDC 16LFCSP |
| 标准包装： | 1 |
| 类型： | 电容数字转换器 |
| 输入类型： | 逻辑 |
| 输出类型： | 逻辑 |
| 接口： | I²C |
| 电流 - 电源： | 1mA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-VQFN 裸露焊盘，CSP |
| 供应商设备封装： | 16-LFCSP-VQ |
| 包装： | 标准包装 |
| 产品目录页面： | 781 (CN2011-ZH PDF) |
| 其它名称： | AD7143ACPZ-1500RL7DKR |
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AD7143
Rev. 0 | Page 14 of 56
CAPACITIANCE-TO-DIGITAL CONVERTER
The capacitance-to-digital converter on the AD7143 has a Σ-Δ
architecture with 16-bit resolution. Eight possible inputs to the
CDC are connected to the input of the converter through a
switch matrix. The sampling frequency of the CDC is 250 kHz.
OVERSAMPLING THE CDC OUTPUT
The decimation rate, or oversampling ratio, is determined by
Bits[9:8] of the PWR_CONTROL register located at Address 0x000
and listed in Table 7.
Table 7. CDC Decimation Rate
Decimation Bit
Value
Decimation
Rate
CDC Output Rate
Per Stage
00
256
3.072 ms
01
128
1.525 ms
–
–
1 Do not use this setting.
The decimation process on the AD7143 is an averaging process
where a number of samples are taken and the averaged result is
output. Due to the architecture of the digital filter employed, the
amount of samples taken (per stage) is equal to 3× the
decimation rate. Therefore, 3 × 256 or 3 × 128 samples are
averaged to obtain each stage result.
The decimation process reduces the amount of noise present in
the final CDC result. However, the higher the decimation rate,
the lower the output rate per stage thus, a trade-off is possible
between a noise free signal and speed of sampling.
CAPACITANCE SENSOR OFFSET CONTROL
There are two programmable DACs on board the AD7143 to
null any capacitance sensor offsets. These offsets are associated
with printed circuit board capacitance or capacitance due to any
capacitance of the input sensors, while CBULK is the capacitance
between layers of the sensor PCB. CBULK can be offset using the
on-board DACs.
PLASTIC OVERLAY
SENSOR BOARD
CBULK
CIN
CAPACITIVE SENSOR
0
6
472
-01
9
Figure 21. Capacitances Around the Sensor PCB
A simplified block diagram in Figure 22 shows how to apply the
STAGE_OFFSET registers to null the offsets. The 7-bit
POS_AFE_OFFSET and NEG_AFE_OFFSET registers program
the offset DAC to provide 0.16 pF resolution offset adjustment
over a range of ±20 pF. Apply the positive and negative offsets
to either the positive or the negative CDC input using the
NEG_AFE_OFFSET register and POS_AFE_OFFSET register.
This process is only required once during the initial capacitance
sensor characterization.
POS_AFE_OFFSET
16-BIT
CDC
NEG_AFE_OFFSET
+DAC
(20pF RANGE)
7
16
CIN
SRC
CIN_CONNECTION_SETUP
REGISTER
SE
N
S
O
R
–DAC
(20pF RANGE)
+
_
0
64
72
-02
0
POS_AFE_OFFSET_SWAP BIT
NEG_AFE_OFFSET_SWAP BIT
Figure 22. Analog Front-End Offset Control
CONVERSION SEQUENCER
The AD7143 has an on-chip sequencer to implement
conversion control for the input channels. Up to eight
conversion stages can be performed in sequence. Each of the
eight conversion stages can measure an input from a different
sensor. By using the Bank 2 registers, each stage can be uniquely
configured to support multiple capacitance sensor interface
requirements. For example, a sensor S1 can be assigned to
STAGE1 and sensor S2 assigned to STAGE2.
The AD7143 on-chip sequence controller provides conversion
control beginning with STAGE0. Figure 23 shows a block diagram of
the CDC conversion stages and CIN inputs. A conversion sequence is
a sequence of CDC conversions starting at STAGE0 and ending at
the stage determined by the value programmed in the
SEQUENCE_STAGE_NUM register. Depending on the number and
type of capacitance sensors used, not all conversion stages are
required. Use the SEQUENCE_STAGE_NUM register to set the
number of conversions in one sequence, depending on the sensor
interface requirements. For example, this register is set to 5 if the CIN
inputs are mapped to only six stages. In addition, set the
STAGE_CAL_EN registers according to the number of stages that
are used.
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