参数资料
型号: AD7143ACPZ-1500RL7
厂商: Analog Devices Inc
文件页数: 9/57页
文件大小: 0K
描述: IC CTLR PROGRAMMABLE CDC 16LFCSP
标准包装: 1
类型: 电容数字转换器
输入类型: 逻辑
输出类型: 逻辑
接口: I²C
电流 - 电源: 1mA
安装类型: 表面贴装
封装/外壳: 16-VQFN 裸露焊盘,CSP
供应商设备封装: 16-LFCSP-VQ
包装: 标准包装
产品目录页面: 781 (CN2011-ZH PDF)
其它名称: AD7143ACPZ-1500RL7DKR
AD7143
Rev. 0 | Page 16 of 56
Low Power Mode CDC Conversion Sequence Time
with Delay
The frequency of each CDC conversion while operating in the
low power automatic wake-up mode is controlled by using the
LP_CONV_DELAY register located at Address 0x000[3:2], in
addition to the registers listed in Table 8.
This feature provides some flexibility for optimizing the
conversion time to meet system requirements vs. AD7143
power consumption. For example, maximum power savings is
achieved when the LP_CONV_DELAY register is set to 3. With
a setting of 3, the AD7143 automatically wakes up, performing a
conversion every 800 ms.
Table 9. LP_CONV_DELAY Settings
LP_CONV_DELAY Bits
Delay Between Conversions
00
200 ms
01
400 ms
10
600 ms
11
800 ms
Figure 26 shows a simplified timing example of the low power
CDC conversion time. As shown, the low power CDC
conversion time is set by tCONV_FP and the LP_CONV_DELAY
register.
CONVERSION
SEQUENCE N
CONVERSION
SEQUENCE N + 1
CDC
CONVERSION
LP_CONV_DELAY
tCONV_LP
tCONV_FP
06
47
2-
0
24
Figure 26. Low Power Mode CDC Conversion Sequence Time
CDC CONVERSION RESULTS
Certain high-resolution sensors require the host to read back
the CDC conversion results for processing. The registers
required for host processing are located in the Bank 3 registers.
The host processes the data readback from these registers using
a software algorithm to determine position information. In
addition to the results registers in the Bank 3 registers, the
AD7143 provides the 16-bit CDC output data directly starting
at Address 0x00B of Bank 1. Reading back the CDC 16-bit
conversion data register allows for customer-specific application
data processing.
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