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| 型号： | AD7147WPACPZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 19/73页 |
| 文件大小： | 0K |
| 描述： | IC CAP-TO-DGTL CONV PROG 24LFCSP |
| 标准包装： | 5,000 |
| 系列： | CapTouch™ |
| 类型： | 电容数字转换器 |
| 分辨率（位）： | 16 b |
| 采样率（每秒）： | 250k |
| 数据接口： | 串行，SPI? |
| 电压电源： | 单电源 |
| 电源电压： | 2.6 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 24-LFCSP-VQ（4x4） |
| 包装： | 带卷 (TR) |
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Data Sheet
AD7147
Rev. D | Page 25 of 72
THRESHOLD EQUATIONS
On-Chip Logic Stage High Threshold
Y
SENSITIVIT
THRESHOLD
POS
HIGH
OFFSET
STAGEx
HIGH
OFFSET
STAGEx
HIGH
OFFSET
STAGEx
AMBIENT
SF
STAGEx
THRESHOLD
HIGH
STAGEx
_
16
4
_
4
_
×
+
+
=
(1)
On-Chip Logic Stage Low Threshold
Y
SENSITIVIT
THRESHOLD
NEG
LOW
OFFSET
STAGEx
LOW
OFFSET
STAGEx
LOW
OFFSET
STAGEx
AMBIENT
SF
STAGEx
THRESHOLD
LOW
STAGEx
_
16
4
_
4
_
×
+
+
=
(2)
CAPACITANCE SENSOR BEHAVIOR WITH
CALIBRATION
The AD7147 on-chip adaptive calibration algorithm prevents
sensor detection errors such as the one shown in Figure 36.
This is achieved by monitoring the CDC ambient levels
and readjusting the initial STAGEx_OFFSET_HIGH and
STAGEx_OFFSET_LOW values according to the amount of
ambient drift measured on each sensor. Based on the new
stage offset values, the internal STAGEx_HIGH_THRESHOLD
and STAGEx_LOW_THRESHOLD values described in
Equation 1 and Equation 2 are automatically updated.
This closed-loop routine ensures the reliability and repeatable
operation of every sensor connected to the AD7147 when they
are subjected to dynamic environmental conditions. Figure 37
shows a simplified example of how the AD7147 applies the
adaptive calibration process, resulting in no interrupt errors
even with changing CDC ambient levels due to dynamic
environmental conditions.
CDC
O
UT
P
UT
CO
DE
S
t
SENSOR 1 INT
ASSERTED
1
2
3
4
5
6
STAGEx_HIGH_THRESHOLD
(POSTCALIBRATED
REGISTER VALUE)
CHANGING ENVIRONMENTAL CONDITIONS
1INITIAL STAGEx_OFFSET_HIGH REGISTER VALUE.
2POSTCALIBRATED REGISTER STAGEx_HIGH_THRESHOLD.
3POSTCALIBRATED REGISTER STAGEx_HIGH_THRESHOLD.
4INITIAL STAGEx_LOW_THRESHOLD.
5POSTCALIBRATED REGISTER STAGEx_LOW_THRESHOLD.
6POSTCALIBRATED REGISTER STAGEx_LOW_THRESHOLD.
CDC AMBIENT
VALUE DRIFTING
STAGEx_LOW_THRESHOLD
(POSTCALIBRATED
REGISTER VALUE)
SENSOR 2 INT
ASSERTED
066
63-
034
Figure 37. Typical Sensor Behavior with Calibration Applied on the Data Path
SLOW FIFO
As shown in Figure 34, there are a number of FIFOs
implemented on the AD7147. These FIFOs are located in
Bank 3 of the on-chip memory. The slow FIFOs are used by the
on-chip logic to monitor the ambient capacitance level from
each sensor.
AVG_FP_SKIP and AVG_LP_SKIP
In Register 0x001, Bits[13:12] are the slow FIFO skip control for
full power mode, AVG_FP_SKIP. Bits[15:14] in the same
register are the slow FIFO skip control for low power mode,
AVG_LP_SKIP, and determine which CDC samples are not
used (skipped) in the slow FIFO. Changing the values of the
AVG_FP_SKIP and AVG_LP_SKIP bits slows down or speeds
up the rate at which the ambient capacitance value tracks the
measured capacitance value read by the converter:
Slow FIFO update rate in full power mode = AVG_FP_SKIP ×
[(3 × Decimation Rate) × (SEQUENCE_STAGE_NUM + 1) ×
(FF_SKIP_CNT + 1) × 4 × 107].
Slow FIFO update rate in low power mode = (AVG_LP_SKIP
+ 1) × [(3 × Decimation Rate) × (SEQUENCE_STAGE_NUM
+ 1) × (FF_SKIP_CNT + 1) × 4 x 107]/[(FF_SKIP_CNT + 1)
+ LP_CONV_DELAY].
The slow FIFO is used by the on-chip logic to track the ambient
capacitance value. The slow FIFO expects to receive samples from
the converter at a rate between 33 ms and 40 ms. AVG_FP_SKIP
and AVG_LP_SKIP are used to normalize the frequency of the
samples going into the FIFO, regardless of how many conversion
stages are in a sequence.
Determining the AVG_FP_SKIP and AVG_LP_SKIP values is
required only once during the initial setup of the capacitance
sensor interface. The recommended values for these settings
when using all 12 conversion stages on the AD7147 are as follows:
AVG_FP_SKIP = 00 = skip three samples
AVG_LP_SKIP = 00 = skip zero samples
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