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| 型号： | AD7195BCPZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/45页 |
| 文件大小： | 0K |
| 描述： | IC AFE 24BIT 4.8K 32LFSP |
| 设计资源： | Precision Weigh Scale Design Using AD7195 with Internal PGA and AC Excitation (CN0155) |
| 标准包装： | 5,000 |
| 位数： | 24 |
| 通道数： | 4 |
| 电压 - 电源，模拟： | 4.75 V ~ 5.25 V |
| 电压 - 电源，数字： | 2.7 V ~ 5.25 V |
| 封装/外壳： | 32-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-WQ（5x5） |
| 包装： | 带卷 (TR) |
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AD7195
Rev. 0 | Page 20 of 44
Table 22. Mode Register Bit Designations
Bit Location
Bit Name
Description
MR23 to MR21
MD2 to MD0
Mode select bits. These bits select the operating mode of the AD7195 (see Table 23).
MR20
DAT_STA
This bit enables the transmission of status register contents after each data register read. When
DAT_STA is set, the contents of the status register are transmitted along with each data register read.
This function is useful when several channels are selected because the status register identifies the
channel to which the data register value corresponds.
MR19, MR18
CLK1, CLK0
These bits select the clock source for the AD7195. Either the on-chip 4.92 MHz clock or an external
clock can be used. The ability to use an external clock allows several AD7195 devices to be synchro-
nized. Also, 50 Hz/60 Hz rejection is improved when an accurate external clock drives the AD7195.
CLK1
CLK0
ADC Clock Source
0
External crystal. The external crystal is connected from MCLK1 to MCLK2.
0
1
External clock. The external clock is applied to the MCLK2 pin.
1
0
Internal 4.92 MHz clock. Pin MCLK2 is tristated.
1
Internal 4.92 MHz clock. The internal clock is available on MCLK2.
MR17, MR16
0
These bits must be programmed with a Logic 0 for correct operation.
MR15
SINC3
Sinc3 filter select bit. When this bit is cleared, the sinc4 filter is used (default value). When this bit is set,
the sinc3 filter is used. The benefit of the sinc3 filter compared to the sinc4 filter is its lower settling time.
For a given output data rate, fADC, the sinc3 filter has a settling time of 3/fADC while the sinc4 filter has a
settling time of 4/fADC when chop is disabled. The sinc4 filter, due to its deeper notches, gives better
50 Hz/60 Hz rejection. At low output data rates, both filters give similar rms noise and similar no
missing codes for a given output data rate. At higher output data rates (FS values less than 5), the
sinc4 filter gives better performance than the sinc3 filter for rms noise and no missing codes.
MR14
0
This bit must be programmed with a Logic 0 for correct operation.
MR13
ENPAR
Enable parity bit. When ENPAR is set, parity checking on the data register is enabled. The DAT_STA bit
in the mode register should be set when the parity check is used. When the DAT_STA bit is set, the
contents of the status register are transmitted along with the data for each data register read.
MR12
0
This bit must be programmed with a Logic 0 for correct operation.
MR11
SINGLE
Single cycle conversion enable bit. When this bit is set, the AD7195 settles in one conversion cycle so
that it functions as a zero-latency ADC. This bit has no effect when multiple analog input channels are
enabled or when the single conversion mode is selected.
MR10
REJ60
This bit enables a notch at 60 Hz when the first notch of the sinc filter is at 50 Hz. When REJ60 is set, a
filter notch is placed at 60 Hz when the sinc filter first notch is at 50 Hz. This allows simultaneous 50 Hz/
60 Hz rejection.
MR9 to MR0
FS9 to FS0
Filter output data rate select bits. The 10 bits of data programmed into these bits determine the filter
cut-off frequency, the position of the first notch of the filter, and the output data rate for the part. In
association with the gain selection, they also determine the output noise (and, therefore, the effective
conversion mode is selected,
Output Data Rate = (MCLK/1024)/FS
where FS is the decimal equivalent of the code in Bit FS0 to Bit FS9 and is in the range 1 to 1023, and
MCLK is the master clock frequency. With a nominal MCLK of 4.92 MHz, this results in an output data
rate from 4.69 Hz to 4.8 kHz. With chop disabled, the first notch frequency is equal to the output data
rate when converting on a single channel. When chop is enabled,
Output Data Rate = (MCLK/1024)/(N × FS)
where FS is the decimal equivalent of the code in Bit FS0 to Bit FS9 and is in the range 1 to 1023, and
MCLK is the master clock frequency. With a nominal MCLK of 4.92 MHz, this results in a conversion rate
from 4.69/N Hz to 4.8/N kHz, where N is the order of the sinc filter. The sinc filter’s first notch frequency
is equal to N × output data rate. The chopping introduces notches at odd integer multiples of (output
data rate/2).
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD7195BCPZ-RL7 | 功能描述:IC AFE 24BIT 4.8K 32LFSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模拟前端 (AFE) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:- 通道数:2 功率（瓦特）:- 电压 - 电源，模拟:3 V ~ 3.6 V 电压 - 电源，数字:3 V ~ 3.6 V 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:带卷 (TR) |
| AD71L | 制造商:Johnson Components 功能描述:ADAPT - Bulk |
| AD72 | 制造商:Distributed By MCM 功能描述:REFRIGERATR DOOR GASKET DIRECT |
| AD720 | 制造商:AD 制造商全称:Analog Devices 功能描述:RGB to NTSC/PAL Encoders |
| AD720-00E | 功能描述:SENSOR MAG SW 28G STANDRD 8-MSOP 制造商:nve corp/sensor products 系列:AD 包装:管件 零件状态:有效 功能:全极开关 技术:霍尔效应 极化:任意一种 感应范围:±3.4mT 跳闸，±1.4mT 释放 测试条件:-40°C ~ 125°C 电压 - 电源:4.5 V ~ 30 V 电流 - 电源（最大值）:4.5mA 电流 - 输出（最大值）:20mA 输出类型:开路集电极 特性:- 工作温度:-40°C ~ 125°C（TA） 封装/外壳:8-TSSOP，8-MSOP（0.118"，3.00mm 宽） 供应商器件封装:8-MSOP 标准包装:1,000 |
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