- 您现在的位置：买卖IC网 > PDF目录373895 > AD7243SQ2 (Analog Devices, Inc.) LC2MOS 12-Bit Serial DACPORT PDF资料下载
参数资料
| 型号： | AD7243SQ2 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | LC2MOS 12-Bit Serial DACPORT |
| 中文描述： | LC2MOS 12位串行DACPORT |
| 文件页数： | 5/12页 |
| 文件大小： | 171K |
| 代理商： | AD7243SQ2 |
REV. A
–5–
AD7243
TERMINOLOGY (Continued)
This “knee” is an offset effect, not a linearity error, and the
transfer function would have followed the dotted line if the out-
put voltage could have gone negative.
Normally, linearity is measured between zero (all 0s input code)
and full scale (all 1s input code) after offset and full scale have
been adjusted out or allowed for, but this is not possible in
single supply operation if the offset is negative, due to the knee
in the transfer function. Instead, linearity of the AD7243 in the
unipolar mode is measured between full scale and the lowest
code which is guaranteed to produce a positive output voltage.
This code is calculated from the maximum specification for
negative offset. For the A and B versions the linearity is mea-
sured between Codes 3 and 4095. For the S grade, linearity is
measured between Code 5 and Code 4095.
Differential Nonlinearity
Differential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of
±
1 LSB or less
over the operating temperature range ensures monotonicity.
Unipolar Offset Error
Unipolar Offset Error is the measured output voltage from
V
OUT
with all zeros loaded into the DAC latch when the DAC is
configured for unipolar output. It is due to a combination of the
offset errors in the DAC and output amplifier.
PIN CONFIGURATION
DIP and SOIC
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
REFIN
REFOUT
CLR
BIN/COMP
SCLK
SDIN
SYNC
DGND
AGND
SDO
DCEN
LDAC
V
DD
V
SS
V
OUT
R
OFS
AD7243
CIRCUIT INFORMATION
D/A Section
The AD7243 contains a 12-bit voltage mode D/A converter
consisting of highly stable thin film resistors and high speed
NMOS single-pole, double-throw switches. The output voltage
from the converter has the same polarity as the reference volt-
age, REFIN, allowing single supply operation.
SHOWN FOR ALL 1S
ON DAC
*BUFFERED REFIN VOLTAGE
2R
2R
R
R
R
R
R
2R
2R
2R
2R
2R
2R
DB0
DB1
DB9
DB10
DB11
REFIN*
AGND
R
OFS
V
OUT
Figure 2. D/A Simplified Circuit Diagram
Internal Reference
The AD7243 has an on-chip temperature compensated buried
Zener reference which is factory trimmed to 5 V
±
50 mV. The
reference voltage is provided at the REFOUT pin. This refer-
ence can be used to provide the reference voltage for the D/A
converter (by connecting the REFOUT pin to the REFIN pin.)
The reference voltage can also be used as a reference for other
components and is capable of providing up to 500
μ
A to an ex-
ternal load. The maximum recommended capacitance on
REFOUT for normal operation is 50 pF. If the reference is re-
quired for external use with capacitive loads greater than 50 pF
then it should be decoupled to AGND with a 200
resistor in
series with a parallel combination of a 10
μ
F tantalum capacitor
and a 0.1
μ
F ceramic capacitor.
200
10 F
0.1 F
REFOUT
EXT
LOAD
Figure 3. Reference Decoupling Scheme
External Reference
In some applications, the user may require a system reference or
some other external reference to drive the AD7243. References
such as the AD586 provide an ideal external reference source
(see Figure 10). The REFIN voltage is internally buffered by a
unity gain amplifier before being applied to the D/A converter.
The D/A converter is scaled for a 5 V reference and the device is
tested with 5 V applied to REFIN. Other reference voltages may
be used with degraded performance. Figure 4 shows the typical
degradation in linearity vs. REFIN.
REFIN – Volts
1.0
2
L
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
3
4
5
6
7
8
9
V
DD
= +15V
V
SS
= –15V
T
A
= +25 C
INL
DNL
Figure 4. Typical Linearity vs. REFIN Voltage
Op Amp Section
The output of the voltage mode D/A converter is buffered by a
noninverting CMOS amplifier. The R
OFS
input allows three out-
put voltage ranges to be selected. The buffer amplifier is capable
of developing +10 V across a 2 k
load to AGND.
The output amplifier can be operated from a single +12 V to
+15 V supply by tying V
SS
= 0 V.
The amplifier can also be operated from dual supplies to allow
an additional bipolar output range of –5 V to +5 V. Dual supplies are
necessary for the bipolar output range but can also be used for
the unipolar ranges to give faster settling time to voltages near
相关PDF资料 |
PDF描述 |
|---|---|
| AD7247A | LC2MOS Dual 12-Bit DACPORTs |
| AD7237A | LC2MOS Dual 12-Bit DACPORTs |
| AD7237AAN | CAPACITOR, 10UF, 50V ELECTROLYTIC, RADIAL |
| AD7237AAR | LC2MOS Dual 12-Bit DACPORTs |
| AD7237ABN | 10K 10-TURN WW 1/4 DIA SHAFT |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD7243SQ883B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:STANDARD MICROCIRCUIT DRAWING |
| AD7244 | 制造商:AD 制造商全称:Analog Devices 功能描述:LC2MOS Dual, Complete, 12-Bit/14-Bit Serial DACs |
| AD7244AQ | 功能描述:IC DAC 14BIT SRL W/REF 24-CDIP RoHS:否 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1,000 系列:- 设置时间:1µs 位数:8 数据接口:串行 转换器数目:8 电压电源:双 ± 功率耗散（最大）:941mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC W 包装:带卷 (TR) 输出数目和类型:8 电压，单极 采样率（每秒）:* |
| AD7244JN | 功能描述:IC DAC 14BIT SRL W/REF 24-DIP RoHS:否 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 标准包装:2,400 系列:- 设置时间:- 位数:18 数据接口:串行 转换器数目:3 电压电源:模拟和数字 功率耗散（最大）:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:36-TFBGA 供应商设备封装:36-TFBGA 包装:带卷 (TR) 输出数目和类型:* 采样率（每秒）:* |
| AD7244JNZ | 功能描述:IC DAC 14BIT SERIAL W/REF 24DIP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 标准包装:1 系列:- 设置时间:4.5µs 位数:12 数据接口:串行，SPI? 转换器数目:1 电压电源:单电源 功率耗散（最大）:- 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOICN 包装:剪切带 (CT) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:* 其它名称:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
发布紧急采购，3分钟左右您将得到回复。