参数资料
| 型号： | AD7244AQ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/12页 |
| 文件大小： | 0K |
| 描述： | IC DAC 14BIT SRL W/REF 24-CDIP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 1 |
| 设置时间： | 4µs |
| 位数： | 14 |
| 数据接口： | 串行 |
| 转换器数目： | 2 |
| 电压电源： | 双 ± |
| 功率耗散（最大）： | 195mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 24-CDIP（0.300"，7.62mm） |
| 供应商设备封装： | 24-CDIP |
| 包装： | 管件 |
| 输出数目和类型： | 2 电压，双极 |
| 采样率（每秒）： | 250k |
AD7242/AD7244
REV. A
–5–
AD7242/AD7244 PIN FUNCTION DESCRIPTION
DIP
Pin No.
Mnemonic
Description
1
LDACA
Load DAC, Logic Input. A new word is transferred into DAC Latch A from input Latch A on the fall-
ing edge of this signal. If LDACA is hard-wired low, data is transferred from input Latch A to DAC
Latch A on the sixteenth falling edge of TCLKA after TFSA goes low.
2
TFSA
Transmit Frame Synchronization, Logic Input. This is a frame or synchronization signal for DACA
data with serial data expected after the falling edge of this signal.
3
DTA
Transmit Data, Logic Input. This is the data input which is used in conjunction with TFSA and
TCLKA to transfer serial data to input Latch A.
4
TCLKA
Transmit Clock, Logic Input. Serial data bits for DACA are latched on the falling edge of TCLKA
when TFSA is low.
5
DGND
Digital Ground. Both DGND pins for the device must be tied together at the device.
6
TP1
Test Pin 1. Used when testing the device. Do not connect anything to this pin.
7VDD
Positive Power Supply, 5 V
± 5%. Both V
DD pins for the device must be tied together at the device.
8
AGND
Analog Ground. Both AGND pins for the device must be tied together at the device.
9VOUTB
Analog Output Voltage from DACB. This output comes from a buffer amplifier. The range is bipolar,
±3 V with REF INB = +3 V.
10
VSS
Negative Power Supply, –5 V
± 5%. Both V
SS pins for the device must be tied together at the device.
11
TP2
Test Pin 2. Used when testing the device. Do not connect anything to this pin.
12
REF INB
DACB Voltage Reference Input. The voltage reference for DACB is applied to this pin. It is internally
buffered before being applied to DACB. The nominal reference voltage for correct operation of the
AD7242/AD7244 is 3 V.
13
LDACB
Load DAC, Logic Input. A new word is transferred into DAC Latch B from input Latch B on the fall-
ing edge of this signal. If LDACB is hard-wired low, data is transferred from input Latch B to DAC
Latch B on the sixteenth falling edge of TCLKB after TFSB goes low.
14
TFSB
Transmit Frame Synchronization, Logic Input. This is a frame or synchronization signal for DACB
data with serial data expected after the falling edge of this signal.
15
DTB
Transmit Data, Logic Input. This is the data input used in conjunction with TFSB and TCLKB to
transfer serial data to input Latch B.
16
TCLKB
Transmit Clock, Logic Input. Serial data bits for DACB are latched on the falling edge of TCLKB
when TFSB is low.
17
DGND
Digital Ground. Both DGND pins for the device must be tied together at the device.
18
TP3
Test Pin 3. Used when testing the device. Do not connect anything to this pin.
19
VDD
Positive Power Supply, 5 V
± 5%. Both V
DD pins for the device must be tied together at the device.
20
AGND
Analog Ground. Both AGND pins for the device must be tied together at the device.
21
VOUTA
Analog Output Voltage from DACA. This output comes from a buffer amplifier. The range is bipolar,
±3 V with REF INA = +3 V.
22
VSS
Negative Power Supply, –5 V
± 5%. Both V
SS pins for the device must be tied together at the device.
23
REF OUT
Voltage Reference Output. To operate the DACs with this internal reference, REF OUT should be
connected to both REF INA and REF INB. The external load capability of the reference is 500
A.
24
REF INA
DACA Voltage Reference Input. The voltage reference for DACA is applied to this pin. It is internally
buffered before being applied to DACA. The nominal reference voltage for correct operation of the
AD7242/AD7244 is 3 V.
相关PDF资料 |
PDF描述 |
|---|---|
| AD7247AQ | IC DAC 12BIT W/AMP W/BUFF 24CDIP |
| AD7248AQ | IC DAC 12BIT W/REF 24-CDIP |
| AD7249BR | IC DAC 12BIT SRL W/REF 16-SOIC |
| AD7262BSTZ | IC ADC 2CH 12BIT PGA/COM 48LQFP |
| AD7264BCPZ | IC ADC 14BIT 2CH 1MSPS 48LFCSP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD7244JN | 功能描述:IC DAC 14BIT SRL W/REF 24-DIP RoHS:否 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 标准包装:2,400 系列:- 设置时间:- 位数:18 数据接口:串行 转换器数目:3 电压电源:模拟和数字 功率耗散（最大）:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:36-TFBGA 供应商设备封装:36-TFBGA 包装:带卷 (TR) 输出数目和类型:* 采样率（每秒）:* |
| AD7244JNZ | 功能描述:IC DAC 14BIT SERIAL W/REF 24DIP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 标准包装:1 系列:- 设置时间:4.5µs 位数:12 数据接口:串行，SPI? 转换器数目:1 电压电源:单电源 功率耗散（最大）:- 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOICN 包装:剪切带 (CT) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:* 其它名称:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD7244JR | 功能描述:IC DAC 14BIT LC2MOS DUAL 28SOIC RoHS:否 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1,000 系列:- 设置时间:1µs 位数:8 数据接口:串行 转换器数目:8 电压电源:双 ± 功率耗散（最大）:941mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC W 包装:带卷 (TR) 输出数目和类型:8 电压，单极 采样率（每秒）:* |
| AD7244JR-REEL | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| AD7244JRZ | 功能描述:IC DAC 14BIT LC2MOS DUAL 28SOIC RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 标准包装:1 系列:- 设置时间:4.5µs 位数:12 数据接口:串行，SPI? 转换器数目:1 电压电源:单电源 功率耗散（最大）:- 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOICN 包装:剪切带 (CT) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:* 其它名称:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
发布紧急采购，3分钟左右您将得到回复。