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参数资料
| 型号： | AD7247AAR |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | DAC |
| 英文描述： | 0.1UF 50V 10% 0805 X7R CERAMIC CAPACITOR |
| 中文描述： | DUAL, PARALLEL, WORD INPUT LOADING, 5 us SETTLING TIME, 12-BIT DAC, PDSO24 |
| 封装： | SOIC-24 |
| 文件页数： | 2/12页 |
| 文件大小： | 392K |
| 代理商： | AD7247AAR |
REV. 0
–2–
AD7237A/AD7247A–SPECIFICATIONS
R
L
= 2 k
, C
L
= 100 pF. All specifications T
MIN
to T
MAX
unless otherwise noted.)
(V
DD
= +12 V to +15 V,
1
V
SS
= 0 V or –12 V to –15 V,
1
AGND =
DGND = 0 V [AD7237A], GND = 0 V [AD7247A], REF IN = +5 V,
Parameter
A
2
B
2
T
2
Units
Test Conditions/Comments
STATIC PERFORMANCE
Resolution
Relative Accuracy
3
Differential Nonlinearity
3
Unipolar Offset Error
3
Bipolar Zero Error
12
±
1
±
0.9
±
3
±
6
12
±
1/2
±
0.9
±
3
±
4
12
±
1/2
±
0.9
±
4
±
6
Bits
LSB max
LSB max
LSB max
LSB max
Guaranteed Monotonic
V
SS
= 0 V or –12 V to –15 V
4
. DAC Latch Contents All 0s
V
= –12 V to –15 V
. DAC Latch Contents
1000 0000 0000
Full-Scale Error
3, 5
Full-Scale Mismatch
5
±
5
±
1
±
5
±
1
±
6
±
1
LSB max
LSB typ
REFERENCE OUTPUT
REF OUT
Reference Temperature
Coefficient
Reference Load Change
(
REF OUT vs.
I)
4.97/5.03
4.97/5.03
4.95/5.05
V min/max
±
25
±
25
±
25
ppm/
°
C typ
–1
–1
–1
mV max
Reference Load Current Change (0-100
μ
A)
REFERENCE INPUT
Reference Input Range
Input Current
4.75/5.25
±
5
4.75/5.25
±
5
4.75/5.25
±
5
V min/max
μ
A max
5 V
±
5%
DIGITAL INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current
I
(Data Inputs)
Input Capacitance
6
2.4
0.8
2.4
0.8
2.4
0.8
V min
V max
±
10
8
±
10
8
±
10
8
μ
A max
pF max
V
IN
= 0 V to V
DD
ANALOG OUTPUTS
Output Range Resistors
Output Voltage Ranges
7
Output Voltage Ranges
7
DC Output Impedance
15/30
+5, +10
+5, +10,
±
5
0.5
15/30
+5, +10
+5, +10,
±
5
0.5
15/30
k
min/max
V
Single Supply; (V
SS
= 0 V)
Dual Supply; (V
SS
= –12 V to –15 V
4
)
+5, +10,
±
5
0.5
typ
AC CHARACTERISTICS
6
Voltage Output Settling Time
Positive Full-Scale Change
Negative Full-Scale Change 8
Settling Time to Within
±
1/2 LSB of Final Value
DAC Latch all 0s to all 1s. Typically 5
μ
s
DAC Latch all 1s to all 0s. Typically 5
μ
s
V
SS
= –12 V to –15 V
.
8
8
8
10
10
μ
s max
μ
s max
Digital-to-Analog Glitch
Impulse
Digital Feedthrough
3
Digital Crosstalk
3
30
10
30
30
10
30
30
10
30
nV secs typ
nV secs typ
nV secs typ
DAC Latch Contents Toggled Between all 0s and all 1s
POWER REQUIREMENTS
V
DD
V
SS
I
DD
I
SS
(Dual Supplies)
+10.8/+16.5 +11.4/+15.75 +11.4/+15.75 V min/max
–10.8/–16.5
–11.4/–15.75 –11.4/–15.75
15
15
5
5
For Specified Performance Unless Otherwise Stated
For Specified Performance Unless Otherwise Stated
Output Unloaded. Typically 10 mA
Output Unloaded. Typically 3 mA
V min/max
mA max
mA max
15
5
NOTES
1
Power Supply tolerance is
±
10% for A version and
±
5% for B and T versions.
2
Temperature ranges are as follows: A, B Versions, –40
°
C to +85
°
C; T Version, –55
°
C to +125
°
C.
3
See Terminology.
4
With appropriate power supply tolerances.
5
Measured with respect to REF IN and includes unipolar/bipolar offset error.
6
Sample tested @ +25
°
C to ensure compliance.
7
0 V to +10 V range is only available with V
DD
≥
14.25 V.
Specifications subject to change without notice.
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