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参数资料
| 型号： | AD724JRZ-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/15页 |
| 文件大小： | 0K |
| 描述： | IC ENCODER RGB TO NTSC 16SOIC TR |
| 标准包装： | 400 |
| 类型： | 视频编码器 |
| 应用： | RGB 至 NTSC/PAL |
| 电压 - 电源，数字： | 4.75 V ~ 5.25 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC W |
| 包装： | 带卷 (TR) |
REV. B
–8–
AD724
THEORY OF OPERATION
The AD724 was designed to have three allowable modes of
applying a clock via the FIN pin. These are FSC (frequency of
subcarrier) mode with CMOS clock applied, FSC mode using
on-chip crystal oscillator, and 4FSC mode with CMOS clock
applied. The FSC frequency is 3.579545 MHz for NTSC or
4.433618 MHz for PAL.
To use FSC mode the SELECT pin is pulled low and either a
CMOS FSC clock is applied to FIN, or a parallel-resonant
crystal and appropriate tuning capacitor is placed between the
FIN pin and AGND to utilize the on-chip oscillator. The on-
chip Phase Locked Loop (PLL) is used in these modes to gener-
ate an internal 4FSC clock that is divided to perform the digital
timing as well as create the quadrature subcarrier signals for the
chrominance modulation.
In 4FSC mode, the SELECT pin is pulled high and the PLL is
bypassed.
Referring to the AD724 block diagram (Figure 14), the RGB
inputs (each 714 mV p-p max) are dc clamped using external
coupling capacitors. These clamps allow the user to have a black
level that is not at 0 V. The clamps will adjust to an on-chip
black input signal level of approximately 0.8 V. This clamping
occurs on the back porch during the burst period.
The RGB inputs then pass into an analog encoding matrix,
which creates the luminance (“Y”) signal and the chrominance
color difference (“U” and “V”) signals. The RGB to YUV en-
coding is performed using the following standard transformations:
Y = 0.299
× R + 0.587 × G + 0.114 × B
U = 0.493
× (B–Y)
V = 0.877
× (R–Y)
After the encoding matrix, the AD724 has two parallel analog
paths. The Y (luminance) signal is first passed through a 3-pole
4.85 MHz/6 MHz (NTSC/PAL) Bessel low-pass filter to pre-
vent aliasing in the sampled-data delay line. In this first low-pass
filter, the unclocked sync is injected into the Y signal. The Y
signal then passes through the sampled-data delay line, which is
clocked at 8FSC. The delay line was designed to match the
overall chrominance and luminance delays. Following the
sampled-data delay line is a 5.25 MHz/6.5 MHz (NTSC/PAL)
2-pole low-pass Bessel filter to smooth the reconstructed lumi-
nance signal.
The second analog path is the chrominance path in which the U
and V color difference signals are processed. The U and V sig-
nals first pass through 4-pole modified Bessel low-pass filters
with –3 dB frequencies of 1.2 MHz/1.5 MHz (NTSC/PAL) to
prevent aliasing in the modulators. The color burst levels are
injected into the U channel for NTSC (U and V for PAL) in
these premodulation filters. The U and V signals are then inde-
pendently modulated by a pair of balanced switching modula-
tors driven in quadrature by the color subcarrier.
The bandwidths of the on-chip filters are tuned using propri-
etary auto-tuning circuitry. The basic principle is to match an
RC time constant to a reference time period, that time being
one cycle of a subcarrier clock. The auto-tuning is performed
during the vertical blanking interval and has added hysteresis so
that once an acceptable tuning value is reached the part won’t
toggle tuning values from field to field. The bandwidths stated
in the above discussion are the design target bandwidths for
NTSC and PAL.
The AD724’s 4FSC clock (either produced by the on-chip PLL
or user supplied) drives a digital divide-by-four circuit to create
the quadrature signals for modulation. The reference phase 0
° is
used for the U signal. In the NTSC mode, the V signal is modu-
lated at 90
°, but in PAL mode, the V modulation alternates
between 90
° and 270° at the horizontal line rate as required by
the PAL standard. The outputs of the U and V balanced modu-
lators are summed and passed through a 3-pole low-pass filter with
3.6 MHz/4.4 MHz bandwidths (NTSC/PAL) in order to re-
move the harmonics generated during the switching modulation.
PHASE
DETECTOR
LOOP
FILTER
4FSC
FSC
SUB-
CARRIER
NTSC/PAL
HSYNC
VSYNC
BURST
NTSC/PAL
FSC 90
FSC 0
4FSC
SC 90 /270
FSC
CSYNC
DC
CLAMP
RED
GREEN
BLUE
RGB-TO-YUV
ENCODING
MATRIX
CSYNC
Y
U
V
4-POLE
LPF
4-POLE
LPF
BALANCED
MODULATORS
4-POLE
LPF
NTSC/PAL
SAMPLED-
DATA
DELAY LINE
X2
LUMINANCE
OUTPUT
COMPOSITE
OUTPUT
CHROMINANCE
OUTPUT
U
CLAMP
CLOCK
AT 8FSC
4FSC
VCO
CHARGE
PUMP
XOSC
XNOR
SYNC
SEPARATOR
QUADRATURE
+4
DECODER
DC
CLAMP
DC
CLAMP
BURST
V
CLAMP
±180
(PAL ONLY)
2-POLE
LP POST-
FILTER
3-POLE
LP PRE-
FILTER
POWER AND GROUNDS
+5V
AGND
DGND
LOGIC
ANALOG
LOGIC
NOTE:
THE LUMINANCE, COMPOSITE, AND
CHROMINANCE OUTPUTS ARE AT
TWICE NORMAL LEVELS FOR DRIVING
75
REVERSE-TERMINATED LINES.
Figure 14. Functional Block Diagram
相关PDF资料 |
PDF描述 |
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| AD724JR-REEL | IC ENCODER RGB TO NTSC 16-SOIC |
| VI-B1N-IY-F1 | CONVERTER MOD DC/DC 18.5V 50W |
| VE-27Y-IX-F3 | CONVERTER MOD DC/DC 3.3V 49.5W |
| VE-26Z-IY-F3 | CONVERTER MOD DC/DC 2V 20W |
| VE-26Z-IX-F1 | CONVERTER MOD DC/DC 2V 30W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD724JRZ-RL | 功能描述:IC ENCODER RGB TO NTSC 16SOIC TR RoHS:是 类别:集成电路 (IC) >> 接口 - 编码器，解码器，转换器 系列:- 产品变化通告:Development Systems Discontinuation 26/Apr/2011 标准包装:1 系列:- 类型:编码器 应用:DVB-S.2 系统 电压 - 电源，模拟:- 电压 - 电源，数字:- 安装类型:- 封装/外壳:模块 供应商设备封装:模块 包装:散装 其它名称:Q4645799 |
| AD725 | 制造商:AD 制造商全称:Analog Devices 功能描述:Low Cost RGB to NTSC/PAL Encoder with Luma Trap Port |
| AD725AR | 制造商:Analog Devices 功能描述:RGB to NTSC and PAL Encoder 16-Pin SOIC W 制造商:Rochester Electronics LLC 功能描述:SOIC LOW COST VIDEO ENCODER - Bulk 制造商:Analog Devices 功能描述:TUBE / SOIC LOW COST VIDEO ENCODER |
| AD725AR-REEL | 制造商:Analog Devices 功能描述:RGB to NTSC and PAL Encoder 16-Pin SOIC W T/R 制造商:Rochester Electronics LLC 功能描述:SOIC LOW COST VIDEO ENCODER - Tape and Reel |
| AD725AR-REEL7 | 制造商:Analog Devices 功能描述:RGB to NTSC and PAL Encoder 16-Pin SOIC W T/R 制造商:Rochester Electronics LLC 功能描述:SOIC LOW COST VIDEO ENCODER - Tape and Reel |
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