参数资料
型号: AD7265BSUZ
厂商: Analog Devices Inc
文件页数: 5/29页
文件大小: 0K
描述: IC ADC 12BIT 3CHAN 1MSPS 32TQFP
设计资源: AD7265 in Differential and Single-Ended Configurations Using AD8022 (CN0048)
标准包装: 1
位数: 12
采样率(每秒): 1M
数据接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 2
功率耗散(最大): 21mW
电压电源: 模拟和数字
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 32-TQFP
供应商设备封装: 32-TQFP(7x7)
包装: 托盘
输入数目和类型: 12 个单端,单极;6 个差分,单极;6 个伪差分,单极
AD7265
Rev. A | Page 12 of 28
The AD7265 is tested using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second-order terms are usually distanced in
frequency from the original sine waves, while the third-order
terms are usually at a frequency close to the input frequencies.
As a result, the second-order and third-order terms are
specified separately. The calculation of the intermodulation
distortion is as per the THD specification, where it is the ratio
of the rms sum of the individual distortion products to the rms
amplitude of the sum of the fundamentals expressed in dBs.
Thermal Hysteresis
Thermal hysteresis is defined as the absolute maximum change
of reference output voltage after the device is cycled through
temperature from either
T_HYS+ = +25°C to TMAX to +25°C
or
T_HYS = +25°C to TMIN to +25°C
It is expressed in ppm by
6
10
)
C
25
(
)
_
(
)
C
25
(
)
(
×
°
°
=
REF
HYS
V
HYS
T
V
ppm
V
Common-Mode Rejection Ratio (CMRR)
CMRR is defined as the ratio of the power in the ADC output at
full-scale frequency, f, to the power of a 100 mV p-p sine wave
applied to the common-mode voltage of V
where:
V
and V
IN+
IN
of
frequency f
REF
(25°C) is VREF at 25°C.
V
S
as
REF
(T_HYS) is the maximum change of VREF at T_HYS+ or
T_HYS.
CMRR (dB) = 10 log(Pf/PfS)
where:
Pf is the power at frequency f in the ADC output.
f
P S is the power at frequency fS in the ADC output.
Power Supply Rejection Ratio (PSRR)
Variations in power supply affect the full-scale transition but
not the converter’s linearity. PSRR is the maximum change in
the full-scale transition point due to a change in power supply
voltage from the nominal value (see Figure 4).
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