参数资料
| 型号： | AD7274BRM |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/29页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 3MSPS HS LP 8MSOP |
| 标准包装： | 50 |
| 位数： | 12 |
| 采样率（每秒）： | 3M |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 18mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 8-MSOP |
| 包装： | 管件 |
| 输入数目和类型： | 1 个单端，单极 |
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AD7273/AD7274
Rev. 0 | Page 21 of 28
SERIAL INTERFACE
for serial interfacing to the AD7274 and AD7273, respectively.
The serial clock provides the conversion clock and controls the
transfer of information from the AD7273/AD7274 during
conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode
and takes the bus out of three-state. The analog input is sampled
and the conversion is initiated at this point.
For the AD7274, the conversion requires completing 14 SCLK
cycles. Once 13 SCLK falling edges have elapsed, the track-and-
hold goes back into track mode on the next SCLK rising edge,
as shown in Figure 36 at Point B. If the rising edge of CS occurs
before 14 SCLKs have elapsed, the conversion is terminated and
the SDATA line goes back into three-state. If 16 SCLKs are
considered in the cycle, the last two bits are zeros and SDATA
returns to three-state on the 16th SCLK falling edge, as shown in
For the AD7273, the conversion requires completing 12 SCLK
cycles. Once 11 SCLK falling edges elapse, the track-and-hold
goes back into track mode on the next SCLK rising edge, as
shown in Figure 38 at Point B. If the rising edge of CS occurs
before 12 SCLKs elapse, the conversion is terminated and the
SDATA line goes back into three-state. If 16 SCLKs are
considered in the cycle, the AD7273 clocks out four trailing
zeros for the last four bits and SDATA returns to three-state on
If the user considers a 14-SCLK cycle serial interface for the
AD7273/AD7274, CS must be brought high after the 14
th SCLK
falling edge. Then the last two trailing zeros are ignored, and
SDATA goes back into three-state. In this case, the 3 MSPS
throughput can be achieved by using a 48 MHz clock frequency.
CS going low clocks out the first leading zero to be read by the
microcontroller or DSP. The remaining data is then clocked out
by subsequent SCLK falling edges, beginning with the second
leading zero. Therefore, the first falling clock edge on the serial
clock provides the first leading zero and clocks out the second
leading zero. The final bit in the data transfer is valid on the 16th
falling edge, because it is clocked out on the previous (15th)
falling edge.
In applications with a slower SCLK, it is possible to read data on
each SCLK rising edge. In such cases, the first falling edge of
SCLK clocks out the second leading zero and can be read on the
first rising edge. However, the first leading zero clocked out
when CS goes low is missed if read within the first falling edge.
The 15th falling edge of SCLK clocks out the last bit and can be
read on the 15th rising SCLK edge.
If CS goes low just after one SCLK falling edge elapses, CS
clocks out the first leading zero and can be read on the SCLK
rising edge. The next SCLK falling edge clocks out the second
leading zero and can be read on the following rising edge.
tCONVERT
TWO LEADING
ZEROS
t2
CS
SCLK
SDATA
THREE-
STATE
THREE-STATE
B
1/THROUGHPUT
1
2
3
4
5
13
14
ZERO
DB11
DB10
DB9
DB1
DB0
Z
t6
t1
tQUIET
t9
t5
t7
t4
t3
04973-036
Figure 36. AD7274 Serial Interface Timing Diagram 14 SCLK Cycle
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD7274BRM-U2 | 制造商:Analog Devices 功能描述:ADC SGL SAR 3MSPS 12-BIT SERL 8MSOP - Bulk |
| AD7274BRMZ | 功能描述:IC ADC 12BIT 3MSPS HS LP 8MSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:12 采样率（每秒）:300k 数据接口:并联 转换器数目:1 功率耗散（最大）:75mW 电压电源:单电源 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC 包装:带卷 (TR) 输入数目和类型:1 个单端，单极；1 个单端，双极 |
| AD7274BRMZ2 | 制造商:AD 制造商全称:Analog Devices 功能描述:3 MSPS,10-/12-Bit ADCs in 8-Lead TSOT |
| AD7274BRMZ-REEL | 功能描述:IC ADC 12BIT 3MSPS HS LP 8MSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:16 采样率（每秒）:45k 数据接口:串行 转换器数目:2 功率耗散（最大）:315mW 电压电源:模拟和数字 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC W 包装:带卷 (TR) 输入数目和类型:2 个单端，单极 |
| AD7274BRMZ-REEL2 | 制造商:AD 制造商全称:Analog Devices 功能描述:3 MSPS,10-/12-Bit ADCs in 8-Lead TSOT |
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