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| 型号： | AD7278AUJZ-RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/29页 |
| 文件大小： | 0K |
| 描述： | IC ADC 8BIT 3MSPS 6TSOT |
| 标准包装： | 3,000 |
| 位数： | 8 |
| 采样率（每秒）： | 3M |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 19.8mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SOT-23-6 细型，TSOT-23-6 |
| 供应商设备封装： | TSOT-23-6 |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个单端，单极 |
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AD7276/AD7277/AD7278
Rev. C | Page 21 of 28
POWER VS. THROUGHPUT RATE
Figure 29 shows the power consumption of the device in
normal mode, in which the part is never powered down. By
using the power-down mode of the AD7276/AD7277/AD7278
when not performing a conversion, the average power consump-
tion of the ADC decreases as the throughput rate decreases.
Figure 30 shows that as the throughput rate is reduced, the
device remains in its power-down state longer, and the average
power consumption over time drops accordingly. For example,
if the AD7276/AD7277/AD7278 are operated in continuous
sampling mode with a throughput rate of 200 kSPS and an SCLK
of 48 MHz (VDD = 3 V) and the devices are placed into power-
down mode between conversions, then the power consumption
is calculated as follows. The power dissipation during normal
operation is 12.6 mW (VDD = 3 V). If the power-up time is one
dummy cycle, that is, 333 ns, and the remaining conversion
time is 290 ns, then the AD7276/AD7277/AD7278 can be said
to dissipate 12.6 mW for 623 ns during each conversion cycle. If
the throughput rate is 200 kSPS, then the cycle time is 5 μs and
the average power dissipated during each cycle is 623/5,000 ×
12.6 mW = 1.56 mW. Figure 29 shows the power vs. throughput
rate when using the partial power-down mode between conver-
sions at 3 V. The power-down mode is intended for use with
throughput rates of less than 600 kSPS, because at higher
sampling rates, there is no power saving achieved by using the
power-down mode.
04
90
3-
02
9
THROUGHPUT (kSPS)
PO
W
E
R
(mW
)
0
3.0
7.4
2000
7.2
7.0
6.8
6.6
6.4
6.2
6.0
5.8
5.6
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
3.4
3.2
200
400
600
800 1000 1200 1400 1600 1800
VARIABLE
SCLK
50MHz SCLK
Figure 29. Power vs. Throughput Normal Mode
04
90
3-
03
5
THROUGHPUT (kSPS)
PO
W
E
R
(mW
)
0
8.0
1000
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
200
400
600
800
VDD =3V
Figure 30. Power vs. Throughput Partial Power-Down Mode
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