参数资料
型号: AD7278AUJZ-RL7
厂商: Analog Devices Inc
文件页数: 18/29页
文件大小: 0K
描述: IC ADC 8BIT 3MSPS 6TSOT
标准包装: 3,000
位数: 8
采样率(每秒): 3M
数据接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
功率耗散(最大): 19.8mW
电压电源: 单电源
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: SOT-23-6 细型,TSOT-23-6
供应商设备封装: TSOT-23-6
包装: 带卷 (TR)
输入数目和类型: 1 个单端,单极
AD7276/AD7277/AD7278
Rev. C | Page 24 of 28
AD7278 IN A 10 SCLK CYCLE SERIAL INTERFACE
For the AD7278, if CS is brought high during the 10
th rising
edge after the two leading zeros and eight bits of the conversion
are provided, then the part can achieve a 4 MSPS throughput
rate. For the AD7278, the track-and-hold goes back into track
mode on the ninth rising edge. In this case, a fSCLK = 48 MHz and
throughput of 4 MSPS result in a cycle time of t2 + 8.5(1/fSCLK) +
tACQ = 250 ns, where t2 = 6 ns minimum and tACQ = 67 ns. This
satisfies the requirement of 60 ns for tACQ.
shows that
tACQ comprises 0.5(1/fSCLK) + t8 + tQUIET, where t8 = 14 ns max.
This allows a value of 43 ns for tQUIET, satisfying the minimum
requirement of 4 ns.
MICROPROCESSOR INTERFACING
AD7276/AD7277/AD7278-to-ADSP-BF53x
The ADSP-BF53x family of DSPs interfaces directly to the
AD7276/AD7277/AD7278 without requiring glue logic. The
SPORT0 Receive Configuration 1 Register should be set up as
outlined in Table 9.
AD7276/
AD7277/
AD7278*
ADSP-BF53x*
SCLK
RCLK0
SPORT0
DR0PRI
RFS0
DT0
DOUT
CS
DIN
*ADDITIONAL PINS OMITTED FOR CLARITY
0
49
03
-09
8
Figure 36. Interfacing with ADSP-BF53x
Table 9. The SPORT0 Receive Configuration 1 Register
(SPORT0_RCR1)
Setting
Description
RCKFE = 1
Sample data with falling edge of RSCLK
LRFS = 1
Active low frame signal
RFSR = 1
Frame every word
IRFS = 1
Internal RFS used
RLSBIT = 0
Receive MSB first
RDTYPE = 00
Zero fill
IRCLK = 1
Internal receive clock
RSPEN = 1
Receive enabled
SLEN = 1111
16-bit data-word (or can be set to 1101 for
14-bit data-word)
TFSR = RFSR = 1
To implement the power-down modes, SLEN should be set to
1001 to issue an 8-bit SCLK burst.
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