参数资料
型号: AD7280ABSTZ
厂商: Analog Devices Inc
文件页数: 6/48页
文件大小: 0K
描述: IC BATT MONITOR LI-ION 48LQFP
标准包装: 1
功能: 电池监控器,过压/欠压保护
电池化学: 锂离子(Li-Ion)
电源电压: 8 V ~ 30 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 48-LQFP
供应商设备封装: 48-LQFP(7x7)
包装: 托盘
AD7280A
TIMING SPECIFICATIONS
V DD = 8 V to 30 V, V SS = 0 V, DV CC = AV CC = V REG , V DRIVE = 2.7 V to 5.5 V, T A = ?40°C to +105°C, unless otherwise noted.
Table 3.
Parameter 1
Min
Typ
Max
Unit
Description
t CONV
ADC conversion time
425
425
560
695
720
ns
ns
?40°C to +85°C
?40°C to +105°C
t ACQ
ADC acquisition time, Bits[D6:D5] of the control register set to 00
340
340
400
465
470
ns
ns
?40°C to +85°C
?40°C to +105°C
t ACQ
ADC acquisition time, Bits[D6:D5] of the control register set to 01
665
665
800
1010
1030
ns
ns
?40°C to +85°C
?40°C to +105°C
t ACQ
ADC acquisition time, Bits[D6:D5] of the control register set to 10
1005
1005
1200
1460
1510
ns
ns
?40°C to +85°C
?40°C to +105°C
t ACQ
ADC acquisition time, Bits[D6:D5] of the control register set to 11
t DELAY
1340
1340
1600
200
1890
1945
250
ns
ns
ns
?40°C to +85°C
?40°C to +105°C
Propagation delay between the falling edges of CNVST of adjacent
parts in the daisy chain
t WAIT
5
μs
Time required between the end of conversions and the beginning
of readback of the conversion results
f SCLK
t QUIET
200
1
MHz
ns
Frequency of serial read clock
Minimum quiet time required between the end of a serial read and
the start of the next conversion
t 1 2
0.4
50
μs
CNVST low pulse
t 2
t 3
t 4
t 6 3
t 7
t 8
t 9
t 10 4
t 11
t 12
10
5
4
20
0.45 × t SCLK
0.45 × t SCLK
100
3
20
28
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
CS falling edge to SCLK rising edge
Delay from CS falling edge until SDO is three-state disabled
SDI setup time prior to SCLK falling edge
SDI hold time after SCLK falling edge
Data access time after SCLK rising edge
SCLK to data valid hold time
SCLK high pulse width
SCLK low pulse width
CS rising edge to SCLK rising edge
CS rising edge to SDO high impedance
CS high time required between each 32-bit write/read command
1
2
3
4
Sample tested during initial release to ensure compliance. All input signals are specified with t R = t F = 5 ns (10% to 90% of V DRIVE ) and timed from a voltage level of 1.6 V.
All timing specifications given are with a 25 pF load capacitance.
Maximum allowed CNVST low pulse time to ensure that a software power-down state is not entered when the CNVST pin is not gated.
Time required for the output to cross 0.4 V or 2.4 V.
t 10 applies when using a continuous SCLK. Guaranteed by design.
Timing Diagram
CS
t 2
t 8
t 10
t 12
SCLK
t 3
1
2
3
t 6
4
t 7
t 9
32
t 11
SDO
THREE-STATE
t 4
MSB
MSB – 1
t 5
LSB
THREE-STATE
SDI
MSB
MSB – 1
LSB
Figure 2. Serial Interface Timing Diagram
Rev. 0 | Page 6 of 48
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