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| 型号： | AD7291BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 17/29页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT SAR 8CH 20-LFCSP |
| 标准包装： | 1 |
| 位数： | 12 |
| 采样率（每秒）： | 22.22k |
| 数据接口： | I²C，串行 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 12.6mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 20-LFCSP-WQ（4x4） |
| 包装： | 托盘 |
| 输入数目和类型： | 8 个单端，单极 |
| 配用： | EVAL-AD7291SDZ-ND - BOARD EVAL FOR AD7291 |
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Data Sheet
AD7291
Rev. B | Page 23 of 28
READING DATA FROM THE AD7291
READING TWO BYTES OF DATA FROM A 16-BIT
REGISTER
Reading the contents from any of the 16-bit registers is a 2-byte
read operation. In this protocol, the first part of the transaction
writes to the register pointer. When the register address has
been set up, any number of reads can be performed from that
particular register without having to write to the address
pointer register again. When the required number of reads
is completed, the master should not acknowledge the final
byte. This tells the slave to stop transmitting, allowing a stop
condition to be asserted by the master. Further reads from
this register can be performed in a future transaction without
having to rewrite to the register pointer.
If a read from a different address is required, the relevant
register address has to be written to the address pointer register
and, again, any number of reads from this register can then be
performed. In the following example, the master device reads
three lots of 2-byte data from a slave device but as many lots
consisting of two bytes can be read as required. This protocol
assumes that the particular register address has been set up by
a single-byte write operation to the address pointer register.
Reading two bytes of data from a 16-bit register consists of the
following sequence (see Figure 27):
1.
The master device asserts a start condition on SDA.
2.
The master sends the 7-bit slave address followed by the
read bit (high).
3.
The addressed slave device asserts an acknowledge on SDA.
4.
The master receives a data byte.
5.
The master asserts an acknowledge on SDA.
6.
The master receives a second data byte.
7.
The master asserts an acknowledge on SDA.
8.
The master receives a data byte.
9.
The master asserts an acknowledge on SDA.
10. The master receives a second data byte.
11. The master asserts an acknowledge on SDA.
12. The master receives a data byte.
13. The master asserts an acknowledge on SDA.
14. The master receives a second data byte.
15. The master asserts a not acknowledge on SDA to notify the
slave that the data transfer is complete.
16. The master asserts a stop condition on SDA to end the
transaction.
087
11
-06
0
S
A
P
...
1
A
SLAVE ADDRESS
DATA[7:0]
DATA[15:8]
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
S = START CONDITION
SR = REPEATED START
P = STOP CONDITION
A = ACKNOWLEDGE
A = NOT ACKNOWLEDGE
Figure 27. Reading Three Lots of Two Bytes of Data from the Conversion Result Register
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