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参数资料
| 型号： | AD7302BNZ |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | DAC |
| 英文描述： | 2.7 V to 5.5 V, Parallel Input Dual Voltage Output 8-Bit DAC |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 1.2 us SETTLING TIME, 8-BIT DAC, PDIP20 |
| 封装： | PLASTIC, DIP-20 |
| 文件页数： | 4/16页 |
| 文件大小： | 292K |
| 代理商： | AD7302BNZ |
AD7302
–12–
REV. 0
MICROPROCESSOR INTERFACING
AD7302–ADSP-2101/ADSP-2103 Interface
Figure 29 shows an interface between the AD7302 and the
ADSP-2101/ADSP-2103. The fast interface timing associated
with the AD7302 allows easy interface to the ADSP-2101/
ADSP-2103.
ADDR
DECODE
DATA BUS
ADDRESS BUS
CS
DB0
DB7
AD7302*
A/B
DMA0
DMA14
WR
EN
DMD0
DMD15
ADSP-2101*/
ADSP-2103*
WR
DMS
A**
A+1**
**ADDITIONAL CIRCUITRY OMITTED FOR CLARITY.
**A DECODED ADDRESS FOR DAC A.
**A+1 DECODED ADDRESS FOR DAC B.
LDAC
Figure 29. AD7302–ADSP-2101/ADSP-2103 Interface
Two addresses are decoded to select loading data to either
DAC A or DAC B.
LDAC is permanently tied low in this
circuit, so the selected DAC output is updated on the rising
edge of the
WR signal.
Data is loaded to the AD7302 input register using the following
ADSP-21xx instruction:
DM (DAC) = MR0
MR0 = ADSP-21xx MR0 Register.
DAC = Decoded DAC Address.
AD7302–TMS32020 Interface
Figure 30 shows an interface between the AD7302 and the
TMS32020. The address decoder is used to decode the
addresses for DAC A and DAC B. Data is loaded to the
AD7302 using the following instruction:
OUT DAC, D
DAC = Decoded DAC Address.
D = Data Memory Address.
ADDR
DECODE
DATA BUS
ADDRESS BUS
CS
DB0
DB7
AD7302*
A/B
A0
A15
STRB
EN
DMD0
DMD15
TMS32020
WR
IS
A**
A+1**
**ADDITIONAL CIRCUITRY OMITTED FOR CLARITY.
**A DECODED ADDRESS FOR DAC A.
**A+1 DECODED ADDRESS FOR DAC B.
LDAC
R/
W
Figure 30. AD7302–TMS32020 Interface
In the circuit shown the
LDAC is hardwired low, thus the
selected DAC output is updated on the rising edge of
WR.
Some applications may require simultaneous updating of both
DACs in the AD7302. In this case the
LDAC signal can be
driven from an external timer or can be controlled by the
microprocessor. One option for simultaneous updating is to
decode the
LDAC from the address bus so that a write opera-
tion at this address will simultaneously update both DAC
outputs. A simple OR gate with one input driven from the
decoded address and the second input from the
WR signal will
implement this function.
AD7302–8051/8088 Interface
Figure 31 shows a serial interface between the AD7302 and the
8051/8088 processors. The address decoder is used to decode
the addresses for DAC A and DAC B.
ADDR
DECODE
ADDRESS/DATA BUS
ADDRESS BUS
DB0
DB7
AD7302*
/B
A8
A15
AD0
AD7
8051/8088
OR
A**
A+1**
**ADDITIONAL CIRCUITRY OMITTED FOR CLARITY.
**A DECODED ADDRESS FOR DAC A.
**A+1 DECODED ADDRESS FOR DAC B.
ALE
OCTAL
LATCH
Figure 31. AD7302–8051//8088 Interface
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| AD7302BR-REEL | 制造商:Analog Devices 功能描述:DAC 2-CH 8-bit 20-Pin SOIC W T/R 制造商:Rochester Electronics LLC 功能描述:3V/5V DUAL 8-BIT DAC I.C. - Tape and Reel |
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| AD7302BRU | 功能描述:IC DAC 8BIT DUAL R-R 20-TSSOP RoHS:否 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 标准包装:2,400 系列:- 设置时间:- 位数:18 数据接口:串行 转换器数目:3 电压电源:模拟和数字 功率耗散（最大）:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:36-TFBGA 供应商设备封装:36-TFBGA 包装:带卷 (TR) 输出数目和类型:* 采样率（每秒）:* |
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