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参数资料
| 型号： | AD73311AR |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 通信及网络 |
| 英文描述： | Low Cost, Low Power CMOS General Purpose Analog Front End |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO20 |
| 封装： | SOIC-20 |
| 文件页数： | 20/36页 |
| 文件大小： | 382K |
| 代理商： | AD73311AR |
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REV. A
AD73311L
–20–
The AD73311L also features direct sampling at the lower rate
of 8 kHz. This is achieved by the use of extended decimation
registers within the decimator block, which allows for the increased
word growth associated with the higher effective oversampling
ratio. Figure 17 details the spectrum of a 1 kHz test tone converted
at an 8 kHz rate.
FREQUENCY
–
Hz
0
500
0
d
50
100
1000
1500
2000
2500
3000
3500
4000
150
Figure 17. FFT (ADC 8 kHz Direct Sampling)
The device features an on-chip master clock divider circuit that
allows the sample rate to be reduced as the sampling rate of the
sigma-delta converter is proportional to the output of the MCLK
Divider (whose default state is divide by 1).
The decimator
’
s frequency response (Sinc3) gives some pass-
band attenuation (up to F
S
/2) which continues to roll off above
the Nyquist frequency. If it is required to implement a digital
fi
lter to create a sharper cutoff characteristic, it may be prudent
to use an initial sample rate of greater than twice the Nyquist
rate in order to avoid aliasing due to the smooth roll-off of the
Sinc3
fi
lter response.
In the case of voiceband processing where 4 kHz represents the
Nyquist frequency, if the signal to be measured were externally
bandlimited, an 8 kHz sampling rate would suf
fi
ce. However, if
it is required to limit the bandwidth using a digital
fi
lter, it may
be more appropriate to use an initial sampling rate of 16 kHz
and to process this sample stream with a
fi
ltering and decimat-
ing algorithm to achieve a 4 kHz bandlimited signal at an 8 kHz
rate. Figure 18 details the initial 16 kHz sampled tone.
FREQUENCY
–
Hz
0
1000
0
–
20
d
–
40
–
60
–
80
–
100
–
120
2000
3000
4000
5000
6000
7000
8000
–
140
Figure 18. FFT (ADC 16 kHz Direct Sampling)
Figure 19 details the spectrum of the
fi
nal 8 kHz sampled
fi
ltered tone.
FREQUENCY Hz
0
500
0
–
20
d
–
40
–
60
–
80
–
100
–
120
1000
1500
2000
2500
3000
3500
4000
–
140
Figure 19. FFT (ADC 8 kHz Filtered and Decimated from
16 kHz)
Encoder Group Delay
When programmed for high sampling rates, the AD73311L
offers a very low level of group delay, which is given by the
following relationship:
Group Delay
(
Decimator
)
= Order
×
((
M – 1
)
/2
)
×
T
DEC
where:
Order
is the order of the decimator (= 3),
M
is the decimation factor (= 32 @ 64 kHz, = 64 @ 32 kHz,
= 128 @ 16 kHz , = 256 @ 8 kHz) and
T
DEC
is the decimation sample interval (= 1/2.048e6) (based
on DMCLK = 16.384 MHz) => Group Delay (Decimator @
64 kHz) = 3
×
(32
–
1)/2
×
(1/2.048e6) = 22.7
μ
s
If
fi
nal
fi
ltering is implemented in the DSP, the
fi
nal
fi
lter
’
s
group delay must be taken into account when calculating overall
group delay.
Decoder Section
The decoder section updates (samples) at the same rate as the
encoder section. This rate is programmable as 64 kHz, 32 kHz,
16 kHz or 8 kHz (from a 16.384 MHz MCLK). The decoder
section represents a reverse of the process that was described in
the encoder section. In the case of the decoder section, signals
are applied in the form of samples at an initial low rate. This
sample rate is then increased to the
fi
nal digital sigma-delta
modulator rate of DMCLK/8 by interpolating new samples
between the original samples. The interpolating
fi
lter also has the
action of canceling images due to the interpolation process using
spectral nulls that exist at integer multiples of the initial sam-
pling rate. Figure 20 shows the spectral response of the decoder
section sampling at 64 kHz. Again, its sigma-delta modulator
shapes the noise so it is reduced in the voice bandwidth dc
–
4kHz.
For improved voiceband SNR, the user can implement an initial
anti-imaging
fi
lter, preceded by 8 kHz to 64 kHz interpolation,
in the DSP.
相关PDF资料 |
PDF描述 |
|---|---|
| AD73311ARS | Low Cost, Low Power CMOS General Purpose Analog Front End |
| AD73311LAR | Low Cost, Low Power CMOS General Purpose Analog Front End |
| AD73311L | Low Cost, Low Power CMOS General Purpose Analog Front End Processor(低成本，低功耗的CMOS通用双模拟前端处理器) |
| AD73311 | Low Cost, Low Power CMOS General Purpose Analog Front End Processor(低成本、低功耗、CMOS通用模拟前端处理器) |
| AD73322LARU | Low Cost, Low Power CMOS General-Purpose Dual Analog Front End |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD73311AR-REEL | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin SOIC W T/R |
| AD73311ARS | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin SSOP |
| AD73311ARS-REEL | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin SSOP T/R 制造商:Rochester Electronics LLC 功能描述:SPEECH & TELEPHONY CODEC I.C. - Tape and Reel |
| AD73311ARSZ | 功能描述:IC ANALOG FRONT END 20-SSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模拟前端 (AFE) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:- 通道数:2 功率（瓦特）:- 电压 - 电源，模拟:3 V ~ 3.6 V 电压 - 电源，数字:3 V ~ 3.6 V 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:带卷 (TR) |
| AD73311ARSZ-REEL | 功能描述:IC ANALOG FRONT END 20-SSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模拟前端 (AFE) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:- 通道数:2 功率（瓦特）:- 电压 - 电源，模拟:3 V ~ 3.6 V 电压 - 电源，数字:3 V ~ 3.6 V 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:带卷 (TR) |
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