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| 型号： | AD73311ARZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/36页 |
| 文件大小： | 0K |
| 描述： | IC PROCESSOR FRONT END LP 20SOIC |
| 标准包装： | 37 |
| 位数： | 16 |
| 通道数： | 2 |
| 功率（瓦特）： | 50mW |
| 电压 - 电源，模拟： | 3V |
| 电压 - 电源，数字： | 3V |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 20-SOIC W |
| 包装： | 管件 |
| 产品目录页面： | 799 (CN2011-ZH PDF) |
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AD73311
–13–
REV. B
FB = 4kHz
FSINIT = DMCLK/8
FB = 4kHz
FSINIT = DMCLK/8
SIGNAL TRANSFER FUNCTION
NOISE TRANSFER FUNCTION
FB = 4kHz FSINTER = DMCLK/256
FB = 4kHz FSFINAL = 8kHz FSINTER = DMCLK/256
a. Analog Antialias Filter Transfer Function
b. Analog Sigma-Delta Modulator Transfer Function
c. Digital Decimator Transfer Function
d. Final Filter LPF (HPF) Transfer Function
Figure 7. AD73311 ADC Frequency Responses
Decimation Filter
The digital filter used in the AD73311 carries out two important
functions. Firstly, it removes the out-of-band quantization noise,
which is shaped by the analog modulator and secondly, it
decimates the high frequency bit-stream to a lower rate 15-bit
word.
The antialiasing decimation filter is a sinc-cubed digital filter
that reduces the sampling rate from DMCLK/8 to DMCLK/
256, and increases the resolution from a single bit to 15 bits. Its
Z transform is given as: [(1–Z
–32)/(1–Z–1)]3. This ensures a
minimal group delay of 25
s.
ADC Coding
The ADC coding scheme is in twos complement format (see
Figure 8). The output words are formed by the decimation
filter, which grows the word length from the single-bit output of
the sigma-delta modulator to a 15-bit word, which is the final
output of the ADC block. In 16-bit Data Mode this value is left
shifted with the LSB being set to 0. For input values equal to or
greater than positive full scale, however, the output word is set
at 0x7FFF, which has the LSB set to 1. In mixed Control/Data
Mode, the resolution is fixed at 15 bits, with the MSB of the
16-bit transfer being used as a flag bit to indicate either control
or data in the frame.
VINN
VINP
VREF + (VREF x 0.32875)
VREF
VREF – (VREF x 0.32875)
10...00
00...00
01...11
ADC CODE DIFFERENTIAL
VINN
VINP
VREF + (VREF x 0.6575)
VREF
VREF – (VREF x 0.6575)
10...00
00...00
01...11
ADC CODE SINGLE ENDED
ANALOG
INPUT
ANALOG
INPUT
Figure 8. ADC Transfer Function
Decoder Channel
The decoder channel consists of a digital interpolator, digital
sigma-delta modulator, a single bit digital-to-analog converter
(DAC), an analog smoothing filter and a programmable gain
amplifier with differential output.
DAC Coding
The DAC coding scheme is in twos complement format with
0x7FFF being full-scale positive and 0x8000 being full-scale
negative.
Interpolation Filter
The anti-imaging interpolation filter is a sinc-cubed digital
filter which up-samples the 16-bit input words from a rate of
DMCLK/256 to a rate of DMCLK/8 while filtering to attenuate
images produced by the interpolation process. Its Z transform is
given as: [(1–Z
–32)/(1–Z–1)]3. The DAC receives 16-bit samples
from the host DSP processor at a rate of DMCLK/256. If the
host processor fails to write a new value to the serial port, the
existing (previous) data is read again. The data stream is filtered
by the anti-imaging interpolation filter, but there is an option to
bypass the interpolator for the minimum group delay configura-
tion by setting the IBYP bit (CRE:5) of Control register E. The
interpolation filter has the same characteristics as the ADC’s
antialiasing decimation filter.
The output of the interpolation filter is fed to the DAC’s digital
sigma-delta modulator, which converts the 16-bit data to 1-bit
samples at a rate of DMCLK/8. The modulator noise-shapes
the signal so that errors inherent to the process are minimized in
the passband of the converter. The bit-stream output of the
sigma-delta modulator is fed to the single bit DAC where it is
converted to an analog voltage.
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相关代理商/技术参数 |
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|---|---|
| AD73311ARZ-REEL | 功能描述:IC PROCESSOR FRONT END LP 20SOIC RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模拟前端 (AFE) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:- 通道数:2 功率（瓦特）:- 电压 - 电源，模拟:3 V ~ 3.6 V 电压 - 电源，数字:3 V ~ 3.6 V 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:带卷 (TR) |
| AD73311L | 制造商:AD 制造商全称:Analog Devices 功能描述:Low Cost, Low Power CMOS General Purpose Analog Front End |
| AD73311LAR | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin SOIC W 制造商:Rochester Electronics LLC 功能描述:SINGLE-CHANNEL AFE I.C. - Bulk |
| AD73311LAR-REEL | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin SOIC W T/R 制造商:Rochester Electronics LLC 功能描述:SINGLE-CHANNEL AFE I.C. - Tape and Reel |
| AD73311LAR-REEL7 | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin SOIC W T/R 制造商:Rochester Electronics LLC 功能描述:SINGLE-CHANNEL AFE I.C. - Tape and Reel |
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