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参数资料
| 型号： | AD73322L |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | KNOB, RT25; Series:29JF RoHS Compliant: Yes |
| 中文描述： | 低成本，低功耗CMOS通用双模拟前端 |
| 文件页数： | 27/40页 |
| 文件大小： | 437K |
| 代理商： | AD73322L |
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AD73322L
–27–
DESIGN CONSIDERATIONS
The AD73322L features both differential inputs and outputs on
each channel to provide optimal performance and avoid com-
mon mode noise. It is also possible to interface either inputs or
outputs in single-ended mode. This section details the choice of
input and output configurations and also gives some tips towards
successful configuration of the analog interface sections.
VFBN1
GAIN
1
+6/
15dB
–
COTIME
LOW-PASS
FILTER
V
REF
VINN1
VINP1
VFBP1
VOUTP1
VOUTN1
REFOUT
REFERENCE
AD73322L
V
REF
AFILTER
100
0.047 F
0.047 F
100
REFCAP
0.1 F
0PGA
Figure 24. Analog Input (DC-Coupled)
Analog Inputs
There are several different ways in which the analog input
(encoder) section of the AD73322L can be interfaced to exter-
nal circuitry. It provides optional input amplifiers which allows
sources with high source impedance to drive the ADC section
correctly. When the input amplifiers are enabled, the input channel
is configured as a differential pair of inverting amplifiers referenced
to the internal reference (REFCAP) level. The inverting termi-
nals of the input amplifier pair are designated as pins VINP1 and
VINN1 for Channel 1 (VINP2 and VINN2 for Channel 2) and
the amplifier feedback connections are available on pins VFBP1
and VFBN1 for Channel 1 (VFBP2 and VFBN2 for Channel 2).
For applications where external signal buffering is required,
the input amplifiers can be bypassed and the ADC driven
directly. When the input amplifiers are disabled, the sigma-
delta modulator
’
s input section (SC PGA) is accessed directly
through the VFBP1 and VFBN1 pins for Channel 1 (VFBP2
and VFBN2 for Channel 2).
It is also possible to drive the ADCs in either differential or
single-ended modes. If the single-ended mode is chosen it is
possible using software control to multiplex between two single-
ended inputs connected to the positive and negative input pins.
The primary concerns in interfacing to the ADC are first to
provide adequate antialias filtering and to ensure that the signal
source will drive the switched-capacitor input of the ADC
correctly. The sigma-delta design of the ADC and its over sam-
pling characteristics simplify the antialias requirements but it
must be remembered that the single pole RC filter is primarily
intended to eliminate aliasing of frequencies above the Nyquist
frequency of the sigma-delta modulator
’
s sampling rate (typi-
cally 2.048 MHz). It may still require a more specific digital filter
implementation in the DSP to provide the final signal frequency
response characteristics. It is recommended that for optimum
performance that the capacitors used for the antialiasing filter be
of high quality dielectric (NPO). The second issue mentioned
above is interfacing the signal source to the ADC
’
s switched
capacitor input load. The SC input presents a complex dynamic
load to a signal source, therefore, it is important to understand
that the slew rate characteristic is an important consideration
when choosing external buffers for use with the AD73322L.
The internal inverting op amps on the AD73322L are specifi-
cally designed to interface to the ADC
’
s SC input stage.
The AD73322L
’
s on-chip 38 dB preamplifier can be enabled
when there is not enough gain in the input circuit; the preampli-
fier is configured by bits IGS0-2 of CRD. The total gain must
be configured to ensure that a full-scale input signal produces a
signal level at the input to the sigma-delta modulator of the
ADC that does not exceed the maximum input range.
The dc biasing of the analog input signal is accomplished with
an on-chip voltage reference. If the input signal is not biased at
the internal reference level (via REFOUT), then it must be
ac-coupled with external coupling capacitors. C
IN
should be
0.1
μ
F or larger. The dc biasing of the input can then be accom-
plished using resistors to REFOUT as in Figures 27 and 28.
VFBN1
GAIN
1
V
REF
VINN1
VINP1
VFBP1
VOUTP1
VOUTN1
REFCAP
REFOUT
REFERENCE
0/38dB
PGA
AD73322L
V
REF
BUFFER
AFILTER
0.1 F
100
0.047
100
F
0.047
F
+6/
15dB
–
CONTIME
LFILTER
Figure 25. Analog Input (DC-Coupled) Using External
Amplifiers
The AD73322L
’
s ADC inputs are biased about the internal
reference level (REFCAP level); therefore, it may be necessary to
bias external signals to this level using the buffered REFOUT
level as the reference. This is applicable in either dc- or ac-coupled
configurations. In the case of dc coupling, the signal (biased to
REFOUT) may be applied directly to the inputs (using ampli-
fier bypass), as shown in Figure 24, or it may be conditioned in
an external op amp where it can also be biased to the reference
level using the buffered REFOUT signal, as shown in Figure
25, or it is possible to connect inputs directly to the AD73322L
’
s
input op amps as shown in Figure 26.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD73322LAR | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 28-Pin SOIC W 制造商:Rochester Electronics LLC 功能描述:SPEECH AND TELEPHONY CODEC I.C. - Bulk |
| AD73322LAR-REEL | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 28-Pin SOIC W T/R 制造商:Rochester Electronics LLC 功能描述:SPEECH AND TELEPHONY CODEC I.C. - Tape and Reel |
| AD73322LARU | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 28-Pin TSSOP 制造商:Rochester Electronics LLC 功能描述:SPEECH AND TELEPHONY CODEC I.C. - Bulk 制造商:Analog Devices 功能描述:IC AUDIO CODEC |
| AD73322LARU-REEL | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 28-Pin TSSOP T/R 制造商:Rochester Electronics LLC 功能描述:SPEECH AND TELEPHONY CODEC I.C. - Tape and Reel |
| AD73322LARUZ | 功能描述:IC PROCESSOR FRONTEND DL 28TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模拟前端 (AFE) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:- 通道数:2 功率（瓦特）:- 电压 - 电源，模拟:3 V ~ 3.6 V 电压 - 电源，数字:3 V ~ 3.6 V 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:带卷 (TR) |
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