AD73411
a
Prelimnary Technical Data
REV. PrA 08/99
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Tel: 781/329-4700
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Fax: 781/326-8703
Analog Devices, Inc., 1998
Low-Power CMOS
Analog Front End wth DSP Mcrocomputer
DATA
TECHNCAL
FEATURES
AFE PERFORMANCE
16-Bit A/D Converter
16-Bit D/A Converter
Programmable Input/Output Sample Rates
77 dB ADC SNR
77 dB DAC SNR
64 kS/s Maximum Sample Rate
–90 dB Crosstalk
Low Group Delay (25
μ
s typ per ADC Channel,
50
μ
s typ per DAC Channel)
Programmable Input/Output Gain
On-Chip Reference
DSP PERFORMANCE
19 ns Instruction Cycle Time @ 3.3 Volts, 52 MIPS
Sustained Performance
AD73411-80
80K Bytes of On-Chip RAM, Configured as 16K Words
Program Memory RAM and 16K Words
Data Memory RAM
AD73411-40
40K Bytes of On-Chip RAM, Configured as 8K Words
Program Memory RAM and 8K Words
Data Memory RAM
GE NE RAL D E SC RIPT ION
T he AD73411 is a single-device incorporating a single analog
front end and a microcomputer optimized for digital signal
processing (DSP) and other high speed numeric processing
applications.
T he AD73411’s analog front end (AFE) section is suitable
for general purpose applications including speech and
telephony. T he AFE section features a 16-bit A/D converter
and a 16-bit D/A converter. Each converter provides 77 dB
signal-to-noise ratio over a
voiceband signal bandwidth.
T he AD73411 is particularly suitable for a variety of applica-
tions in the speech and telephony area including low bit rate,
high quality compression, speech enhancement, recognition
and synthesis. T he low group delay characteristic of the AFE
makes it suitable for single or multichannel active control
applications. T he A/D and D/A conversion channels feature
programmable input/ouput gains with ranges 38 dB and 21
dB respectively. An on-chip reference voltage is included
to allow single supply operation.
F UNC T IONAL BL OC K D IAGRAM
ADC
DAC
EXTERNAL
ADDRESS
BUS
HOST MODE
SERIAL PORTS
SPORT 0
SHIFTER
MAC
ALU
ARITHMETIC UNITS
MEMORY
PROGRAMMABLE
I/O
AND
FLAGS
BYTE DMA
CONTROLLER
TIMER
ADSP-2100 BASE
ARCHITECTURE
POWER-DOWN
CONTROL
PROGRAM
SEQUENCER
DAG 2
DATA
ADDRESS
GENERATORS
DAG 1
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
INTERNAL
DMA
PORT
16K DM
(OP8K)
16K PM
(OP8K)
EXDATA
BUS
FULL MEMORY
MODE
OR
EXDATA
BUS
SPORT 1
SERIAL PORT
SPORT 2
REF
ANALOG FRONT END
SECTION
T he sampling rate of the AFE is programmable with four
separate settings offering 64, 32, 16 and 8 kHz sampling rates
(from a master clock of 16.384 MHz) while the serial port
(SPORT 2) allows easy expansion of the number of I/O
channels by cascading extra AFEs external to the AD73411.
T he AD73411’s DSP engine combines the ADSP-2100
family base architecture (three computational units, data
address generators and a program sequencer) with two serial
ports, a 16-bit internal DMA port, a byte DMA port, a
programmable timer, Flag I/O, extensive interrupt capabilities
and on-chip program and data memory.
T he AD73411-80 integrates 80K bytes of on-chip memory
configured as 16K words (24-bit) of program RAM, and 16K
words (16-bit) of data RAM. T he AD73411-40 integrates
40K bytes of on-chip memory configured as 8K words (24-
bit) of program RAM, and 8K words (16-bit) of data RAM.
Power-down circuitry is also provided to meet the low power
needs of battery operated portable equipment. T he AD73411
is available in a 119-ball PBGA package.