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参数资料
| 型号： | AD73322LAR |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 通信及网络 |
| 英文描述： | Low Cost, Low Power CMOS General-Purpose Dual Analog Front End |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO28 |
| 封装： | MS-013AE, SOIC-28 |
| 文件页数： | 9/40页 |
| 文件大小： | 437K |
| 代理商： | AD73322LAR |
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REV. 0
AD73322L
–9–
TERMINOLOGY
Absolute Gain
Absolute gain is a measure of converter gain for a known signal.
Absolute gain is measured (differentially) with a 1 kHz sine wave at
0 dBm0 for the DAC and with a 1 kHz sine wave at 0 dBm0 for
the ADC. The absolute gain specification is used for gain track-
ing error specification.
Crosstalk
Crosstalk is due to coupling of signals from a given channel to
an adjacent channel. It is defined as the ratio of the amplitude of
the coupled signal to the amplitude of the input signal. Crosstalk
is expressed in dB.
Gain Tracking Error
Gain tracking error measures changes in converter output for
different signal levels relative to an absolute signal level. The
absolute signal level is 0 dBm0 (equal to absolute gain) at 1 kHz
for the DAC and 0 dBm0 (equal to absolute gain) at 1 kHz for
the ADC. Gain tracking error at 0 dBm0 (ADC) and 0 dBm0
(DAC) is 0 dB by definition.
Group Delay
Group Delay is defined as the derivative of radian phase with
respect to radian frequency, d
(f)/df. Group delay is a measure
of average delay of a system as a function of frequency. A linear
system with a constant group delay has a linear phase response.
The deviation of group delay from a constant indicates the
degree of nonlinear phase response of the system.
Idle Channel Noise
Idle channel noise is defined as the total signal energy measured
at the output of the device when the input is grounded (mea-
sured in the frequency range 300 Hz
–
3400 Hz).
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa
±
nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n is equal to zero. For final testing, the second
order terms include (fa + fb) and (fa
–
fb), while the third order
terms include (2fa + fb), (2fa
–
fb), (fa + 2fb) and (fa
–
2fb).
Power Supply Rejection
Power supply rejection measures the susceptibility of a device to
noise on the power supply. Power supply rejection is measured
by modulating the power supply with a sine wave and measuring
the noise at the output (relative to 0 dB).
Sample Rate
The sample rate is the rate at which the ADC updates its output
register and the DAC updates its output from its input register.
The sample rate can be chosen from a list of four that are fixed
relative to the DMCLK. Sample rate is set by programming bits
DIR0-1 in Control Register B of each channel.
SNR+THD
Signal-to-noise ratio plus harmonic distortion is defined to be
the ratio of the rms value of the measured input signal to the
rms sum of all other spectral components in the frequency range
300 Hz
–
3400 Hz, including harmonics but excluding dc.
ABBREVIATIONS
ADC
AFE
AGT
ALB
BW
CRx
Analog-to-Digital Converter.
Analog Front End.
Analog Gain Tap.
Analog Loop-Back.
Bandwidth.
A Control Register where
x
is a placeholder for an
alphabetic character (A
–
E). There are five read/
write control registers on the AD73322L
—
desig-
nated CRA through CRE.
A bit position, where
n
is a placeholder for a nu-
meric character (0
–
7), within a control register,
where
x
is a placeholder for an alphabetic charac-
ter (A
–
E). Position 7 represents the MSB and
Position 0 represents the LSB.
Digital-to-Analog Converter.
Digital Gain Tap.
Digital Loop-Back.
Device (Internal) Master Clock. This is the inter-
nal master clock resulting from the external master
clock (MCLK) being divided by the on-chip mas-
ter clock divider.
Full Scale.
Frame Sync Loop-Back
—
where the SDOFS of
the final device in a cascade is connected to the
RFS and TFS of the DSP and the SDIFS of
first device in the cascade. Data input and out-
put occur simultaneously. In the case of NonFSLB,
SDOFS and SDO are connected to the Rx Port
of the DSP while SDIFS and SDI are connected
to the Tx Port.
Programmable Gain Amplifier.
Switched Capacitor.
Sport Loop-Back.
Signal-to-Noise Ratio.
Serial Port.
Total Harmonic Distortion.
Voice Bandwidth.
CRx:n
DAC
DGT
DLB
DMCLK
FS
FSLB
PGA
SC
SLB
SNR
SPORT
THD
VBW
相关PDF资料 |
PDF描述 |
|---|---|
| AD73322LAST | Low Cost, Low Power CMOS General-Purpose Dual Analog Front End |
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| AD73322EZ | Precision Rail-to-Rail Input and Output Op Amp; Package: SO; No of Pins: 8; Temperature Range: 0°C to +70°C |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD73322LAR-REEL | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 28-Pin SOIC W T/R 制造商:Rochester Electronics LLC 功能描述:SPEECH AND TELEPHONY CODEC I.C. - Tape and Reel |
| AD73322LARU | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 28-Pin TSSOP 制造商:Rochester Electronics LLC 功能描述:SPEECH AND TELEPHONY CODEC I.C. - Bulk 制造商:Analog Devices 功能描述:IC AUDIO CODEC |
| AD73322LARU-REEL | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 28-Pin TSSOP T/R 制造商:Rochester Electronics LLC 功能描述:SPEECH AND TELEPHONY CODEC I.C. - Tape and Reel |
| AD73322LARUZ | 功能描述:IC PROCESSOR FRONTEND DL 28TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模拟前端 (AFE) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:- 通道数:2 功率（瓦特）:- 电压 - 电源，模拟:3 V ~ 3.6 V 电压 - 电源，数字:3 V ~ 3.6 V 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:带卷 (TR) |
| AD73322LARUZ-REEL | 功能描述:IC PROCESSOR FRONTEND DL 28TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模拟前端 (AFE) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:- 通道数:2 功率（瓦特）:- 电压 - 电源，模拟:3 V ~ 3.6 V 电压 - 电源，数字:3 V ~ 3.6 V 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:带卷 (TR) |
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