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| 型号： | AD73322LYR |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 通信及网络 |
| 英文描述： | Low Cost, Low Power CMOS General-Purpose Dual Analog Front End |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO28 |
| 封装： | MS-013AE, SOIC-28 |
| 文件页数： | 34/40页 |
| 文件大小： | 437K |
| 代理商： | AD73322LYR |
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REV. 0
AD73322L
–34–
APPENDIX A
DAC Timing Control Example
The AD73322L
’
s DAC is loaded from the DAC register con-
tents just before the ADC register contents are loaded to the
serial register (SDOFS going high). This default DAC load
position can be advanced in time to occur earlier with respect to
the SDOFS going high. Figure 45 shows an example of the
ADC unload and DAC load sequence. At time t
1
the SDOFS is
raised to indicate that a new ADC word is ready. Following the
SDOFS pulse, 16 bits of ADC data are clocked out on SDO in
the subsequent 16 SCLK cycles finishing at time t
2
where the
DSP
’
s SPORT will have received the 16-bit word. The DSP
may process this information and generate a DAC word to be
sent to the AD73322L. Time t
3
marks the beginning of the
sequence of sending the DAC word to the AD73322L. This
sequence ends at time t
4
where the DAC register will be updated
from the 16 bits in the AD73322L
’
s serial register. However,
the DAC will not be updated from the DAC register until time
t
5
, which may not be acceptable in certain applications. In order
to reduce this delay and load the DAC at time t
6
, the DAC
advance register can be programmed with a suitable setting
corresponding to the required time advance (refer to Table X
for details of DAC Timing Control settings).
SE
SCLK
SDOFS
SDO
SDIFS
DATA REGISTER
UPDATE
DAC LOAD
FROM DAC REGISTER
t
1
t
2
t
3
t
4
t
6
t
5
ADC WORD
SDI
DAC WORD
Figure 39. DAC Timing Control
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相关代理商/技术参数 |
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| AD73322LYR-REEL | 制造商:Analog Devices 功能描述: |
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