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参数资料
| 型号： | AD7356YRUZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 9/21页 |
| 文件大小： | 0K |
| 描述： | IC ADC DUAL 12BIT 5MSPS 16TSSOP |
| 设计资源： | DC-Coupled, Single-Ended-to-Differential Conversion Using AD8138 and AD7356 (CN0041) |
| 标准包装： | 2,500 |
| 位数： | 12 |
| 采样率（每秒）： | 50k |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 59mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 2 个差分，双极 |
AD7356
Rev. A | Page 16 of 20
FULL POWER-DOWN MODE
Full power-down mode is intended for use in applications
where throughput rates slower than those in partial power-
down mode are required because power-up from a full power-
down takes substantially longer than that from a partial power-
down. This mode is more suited to applications in which a
series of conversions performed at a relatively high throughput
rate are followed by a long period of inactivity and, thus, power-
down. When the AD7356 is in full power-down mode, all
analog circuitry is powered down including the on-chip
reference and reference buffers. Full power-down mode is
entered in a similar way as partial power-down mode, except
that the timing sequence shown in Figure 25 must be executed
twice. The conversion process must be interrupted in a similar
fashion by bringing CS high anywhere after the second falling
edge of SCLK and before the 10th falling edge of SCLK. The
device enters partial power-down mode at this point.
To reach full power-down, the next conversion cycle must be
interrupted in the same way, as shown in Figure 27. When CS is
brought high in this window of SCLKs, the part fully powers
down.
Note that it is not necessary to complete the 14 or 16 SCLKs
once CS has been brought high to enter a power-down mode.
To exit full power-down mode and power-up the AD7356,
perform a dummy conversion, similar to powering up from
partial power-down. On the falling edge of CS, the device begins
to power up as long as CS is held low until after the falling edge
of the 10th SCLK. The required power-up time must elapse
before a conversion can be initiated, as shown in
.
SCLK
CS
SDATAA
SDATAB
INVALID DATA
VALID DATA
110
14
1
THE PART BEGINS
TO POWER UP.
tPOWER-UP1
0
650
5-
02
0
THE PART IS FULLY POWERED UP;
SEE THE POWER-UP TIMES SECTION.
Figure 26. Exiting Partial Power-Down Mode
THREE-STATE
110
14
2
SCLK
CS
SDATAA
SDATAB
THREE-STATE
110
2
INVALID DATA
THE PART BEGINS
TO POWER UP.
THE PART ENTERS
PARTIAL POWER-DOWN MODE.
THE PART ENTERS
FULL POWER-DOWN MODE.
14
06
50
5-
02
1
Figure 27. Entering Full Power-Down Mode
SCLK
SDATAA
SDATAB
INVALID DATA
VALID DATA
1
10
14
1
THE PART BEGINS
TO POWER UP.
THE PART IS FULLY POWERED UP;
SEE THE POWER-UP TIMES SECTION.
tPOWER-UP2
CS
06
50
5-
0
22
Figure 28. Exiting Full Power-Down Mode
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD7357 | 制造商:AD 制造商全称:Analog Devices 功能描述:Differential Input, Dual, Simultaneous Sampling, 4.2 MSPS, 14-Bit, SAR ADC |
| AD7357_08 | 制造商:AD 制造商全称:Analog Devices 功能描述:Differential Input, Dual, Simultaneous Sampling, 4.2 MSPS, 14-Bit, SAR ADC |
| AD7357_09 | 制造商:AD 制造商全称:Analog Devices 功能描述:Differential Input, Dual, Simultaneous Sampling, 4.2 MSPS, 14-Bit, SAR ADC |
| AD7357BCPZ | 功能描述:14 Bit Analog to Digital Converter 2 Input 2 SAR 18-LFCSP-WQ (5x4) 制造商:analog devices inc. 系列:- 包装:托盘 零件状态:有效 位数:14 采样率（每秒）:4.2M 输入数:2 输入类型:差分 数据接口:SPI，DSP 配置:S/H-ADC 无线电 - S/H:ADC:1:1 A/D 转换器数:2 架构:SAR 参考类型:外部， 内部 电压 - 电源，模拟:2.25 V ~ 2.75 V 电压 - 电源，数字:2.25 V ~ 2.75 V 特性:同步采样 工作温度:-40°C ~ 85°C 封装/外壳:18-WQFN 裸露焊盘，CSP 供应商器件封装:18-LFCSP-WQ（5x4） 标准包装:1 |
| AD7357BCPZ-RL | 功能描述:14 Bit Analog to Digital Converter 2 Input 2 SAR 18-LFCSP-WQ (5x4) 制造商:analog devices inc. 系列:- 包装:带卷（TR） 零件状态:有效 位数:14 采样率（每秒）:4.2M 输入数:2 输入类型:差分 数据接口:SPI，DSP 配置:S/H-ADC 无线电 - S/H:ADC:1:1 A/D 转换器数:2 架构:SAR 参考类型:外部， 内部 电压 - 电源，模拟:2.25 V ~ 2.75 V 电压 - 电源，数字:2.25 V ~ 2.75 V 特性:同步采样 工作温度:-40°C ~ 85°C 封装/外壳:18-WQFN 裸露焊盘，CSP 供应商器件封装:18-LFCSP-WQ（5x4） 标准包装:5,000 |
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